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We have developed an image sensor with thin organic photoconductive film (OPF) laminated on CMOS circuits. Owing to high capacity of a charge storage node, the saturation level is 12 dB higher than those of conventional image sensors. Because of the very thinness of the laminated film, i.e. 0.5 µm, the device is crosstalk-free and an incident light angle of over 30 degrees is realized.
Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes...
The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with...
As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar...
While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had...
For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame...
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed.
We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% bead at Vdd=lV and 0.6V, respectively vs 28LP bulk. Additionally, −100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative...
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVµm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVµm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing...
For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
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