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A serial I/O receiver efficiently implements a decision feedback equalizer (DFE) employing 2 IIR taps for improved long-tail ISI cancellation. The use of a modified multi-input two-stage slicer allows for both DFE summation to be performed directly at the slicer and optimization of the first-tap IIR filter/mux feedback path to allow for cancellation of the critical first post-cursor. Fabricated in...
A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm2 core ADC area.
A SerDes operating from 8.5 to 11.4 Gb/s using nearly all CMOS digital circuits is presented. The transmitter achieves up to 1 Vdpp output swing with a DDJ as low as 2.7 ps. The receiver achieves an input sensitivity of less than 17 mVdpp. The chip is capable of transmitting and receiving data on an FR4 channel with 21 dB loss at Nyquist at a BER < 10−12. The power consumption per Tx/Rx pair is...
A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW...
A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows...
This paper presents a turbo-decoder ASIC for 3GPP LTE-Advanced supporting all specified code rates and block sizes. The highly parallelized architecture employs 16 SISO decoders with an optimized state-metric initialization scheme that reduces SISO-decoder latency, which is key for achieving very-high throughput. A novel CRC implementation for parallel turbo decoding prevents the decoder from performing...
A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range...
This paper presents a new search scheme that reduces the energy dissipation of a lookup engine by reducing the number of rules to compare. The lookup engine with the proposed scheme fabricated in 40-nm CMOS reduces the energy dissipation by 96.5% including only 0.5% overhead.
Fast boosting of supply rails is critical for near-threshold computing to overcome serial code bottlenecks. A novel supply boosting technique, called Shortstop, boosts a 3nF core in 26ns while maintaining acceptable supply voltage droops. The innate parasitic inductance of a dedicated dirty supply rail is used as a boost-converter and combined with an on-chip boost capacitor. Shortstop boosts a core...
This work presents a novel 77GHz automotive radar providing detection distance and angle up to 100m and ±8°, respectively. Using a 1TX/4RX array, this radar system employs various mmWave techniques to fulfill the expected SNR.
A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming calibration is achieved by sequentially performing gain equalization, I/Q calibration, and successive-approximation phase tuning. Implemented in 65nm CMOS, each element measures NF of 6.5dB, gain of 20dB and IP1dB of −12.5dBm. With the proposed beam-forming...
This paper presents a 160GHz center frequency pulsed transmitter for short range radar applications. An array of four transmitters was implemented in a single chip with antennas implemented on the package. Each transmitter can be independently phase shifted, allowing transmit beamforming. The implemented transmitter is capable of producing pulses of 100ps wide (>20GHz RF bandwidth) with 160GHz...
A direct-conversion transceiver including base-band amplifiers and filters employs a 60-GHz quadrature VCO and a feedforward divider with no buffers to achieve a low power consumption. Designed in 40-nm LP CMOS, the radio presents a noise figure of 4.8 to 8.2 dB in the receive mode and an output power of +10 dBm in the transmit mode while drawing 56 mW and 124 mW, respectively.
The Symposium on VLSI Circuits is sponsored by the Japan Society of Applied Physics and the IEEE Solid-State Circuits Society, in cooperation with the Institute of Electronics, Information and Communication Engineers of Japan.
A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >100µs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process...
We demonstrate for the first time, Si1−xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance...
Highly-strained Ge-in-STI pFETs on SiGe55% SRBs are demonstrated with mobilities up to 550 cm2/Vs and record NBTI reliability at TINV∼1.7 nm. Short channel sGe pFET devices down to 35nm gate length are also reported. This work makes the first use of a germanide in contacts to solve void issues and a high Ge (75%) SiGe S/D for strain enhancement of mobility with an RMG flow providing module learning...
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