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This paper presents a fully-integrated bidirectional SC ladder converter in 0.13µm 1.2V/3.3V triple-well CMOS with peak output voltage of ∼10V. The converter actively drives a 5nF mm-sized piezo-electric robotic wing while following <500Hz arbitrary waveforms at ∼3x step-up conversion. High voltage drive signals for the power switches are developed using a new voltage-distributed nested-bootstrapping...
A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14KB register file (RF) load with an area overhead of 3.6% is demonstrated in 22nm tri-gate CMOS. The all-digital, multi-conversion-mode SCVR provides a wide output voltage range of 0.45–1V from a fixed input voltage of 1.225V. It achieves 63–84% conversion efficiency and supports...
A vision chip operating with 1.9pJ/OP efficiency has been fabricated in 0.18µm CMOS. Each of the 256×256 pixel-processors (dimensions 32×32µm), contains 14 binary and 7 analog registers coupled to a photodiode, an arithmetic logic unit, diffusion and asynchronous propagation networks. At the chip's periphery, facilities exist to allow pixel address extraction, analog or digital readout. The chip has...
A fast and accurate Approximate Nearest Neighbor (ANN) searching processor is proposed to resolve the main bottleneck of the real-time object recognition process, the ANN searching. A new scheme, Spatio-Temporal Locality searching (STL-searching), is proposed to reduce the external memory bandwidth by at least 78x compared to Locality Sensitive Hash (LSH) scheme. However, the STL-searching suffers...
This paper proposes a 0.18um CMOS vision sensor that combines event-driven asynchronous readout of temporal contrast with synchronous frame-based active pixel sensor readout of intensity. The sensor is suitable for mobile applications because it allows low latency at low data rate and therefore, low system-level power consumption. The image frames can be used for scene analysis and the temporal contrast...
A single-chip HEVC (H.265) 8192×4320p encoder is implemented on a 25mm2 die with 28nm process. It dissipates 708mW at 312MHz for 8192×4320p encoding. Frame-level pipelining reduces 8.90 GB/s external memory bandwidth and improve CABAC rate by 50%. A 7.14MB three-level memory hierarchy is designed to support internal 43.38 GB/s bandwidth and 13-port accesses, and reduces external reference frame bandwidth...
An All-Digital PLL (ADPLL) in 28 nm CMOS is designed to generate low noise clocks for high-speed ADCs. A high-resolution (< 1 ps), short-span (6 ps) Time-to-Digital Converter (TDC) is implemented to improve the phase noise with little cost of power and area. This ADPLL has < 230 fs RMS jitter at 50 MHz reference frequency, with 8.5 mW power from 1.8V supply and an area of 0.07 mm2.
An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.
A digital LC PLL in a 40nm CMOS technology achieves a 100ns lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° phase error up to 25GHz. Fast lock is achieved by calibrating the phase of the feedback clock. The 8-phase output clock is generated using a loop of four digitally-controlled magnetically-coupled LC oscillators. The architecture is suitable for fast-wakeup...
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is −110dBc/Hz at 10MHz offset. The 140×160µm2 32nm SOI CMOS PLL locks from...
A novel ultra-low-power MCU is presented, which is optimized for both lowest stand-by and active power consumption. By modifying technology, adopting critical blocks in circuit design, and tailoring the system architecture the MCU achieves an overall stand-by current consumption of 350nA. This number includes the real time clock functionality, the 32kHz crystal oscillator, and the supply voltage supervision...
A non-volatile CBRAM macro embedded with a body sensor node processing platform operates at low voltages down to 600mV for write and 300mV for read, enabling ultra low energy operation, compatibility with energy constrained digital systems, and no need for charge pumps.
This paper proposes a Triple-Wire-Program-Cell (TWPC) scheme and Triple-Line-Decoder (TLD) for high density MROM. TWPC consists of a cell transistor with triple wires (bit lines) and stores two-bit data in a cell. These designs have been implemented in 40nm test chips without cell array area overhead. The access time is improved by 38% with TWPC scheme in 40nm 1Mbit macro.
An OSE-less [Oxide-definition Space Effect less] twin bits ROM cell is proposed. A reduced layout proximity dependence effect in ROM array is proposed using an OSE-less twin bits ROM cell. A Two-Step Decoding circuitry scheme suitable for either single-end or differential sensing is invented to read out twin bits ROM data. This work improves access time by 30% and reduces Vccmin by 190mV with TSMC...
Large-area electronics (LAE) enables diverse transducers on large, flexible substrates (∼10m2), making possible expansive sensor arrays and energy harvesting devices. We present a second-generation system for high-resolution structural-health monitoring of bridges achieved by combining LAE with CMOS ICs in a scalable architecture. It aims to enable strain sensing scalable down to cm-resolution over...
A true remote junction temperature sensor (RTS) with 3σ accuracy of 0.4 degrees over a temperature range of −40 to 130 degrees is presented. Using a novel digital beta compensation technique and series resistance cancellation (SRC), the sensor is capable of handling parasitic BJTs buried in other SoCs on a PCB located at large distances. The IC is manufactured in a 65nm digital CMOS process.
A high SNR capacitive touch screen panel (TSP) readout IC is designed. In this paper, Orthogonal Frequency Division Multiple Sensing method is proposed to enhance frame scan rate. Capacitor-less Trans-Impedance Amplifier and Direct Digital Frequency Synthesizer based on Harmonic Rejection Ratio DAC is proposed to save chip area. The prototype IC with 0.18um CMOS achieves 70dB SNR for a finger and...
In this paper, an integrated pulse wave velocity (PWV) sensor that adapts ECG and Bio-impedance (BI) method is proposed. PWV is calculated by measuring the time-difference between the signals from ECG sensor on chest and BI sensor on wrist. To gather these two signals without any cumbersome wires over the body, a noise-shaped body-channel communication method using analog frequency modulation is proposed...
An integrated lab-on-chip capable of performing quantitative polymerase chain reaction (qPCR) is demonstrated in a high-voltage 0.35-µm CMOS process operating at a 3.3 V supply. PCR thermal cycling can be performed by physically moving droplets between three distinct temperature zones on the surface of chip or by thermal cycling a droplet in place. Droplet actuation is enabled by electrowetting-on-dielectric...
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