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Impacts of channel doping concentration on single-trap and multiple-trap random telegraph signal (RTS) noise are studied comprehensively in this work, including trap time constants, current fluctuation (ΔId/Id), and threshold voltage shift (ΔVth_rts). It is found that, higher channel doping not only degrades ΔId/Id and ΔVth_rts, but also enhances couplings between gate bias and trap time constants,...
The AC random telegraph noise (AC RTN) in scaled multi-gate FETs (MuGFETs) is experimentally studied for the first time, which is found to have enhanced AC noise activity than planar FETs. A new AC RTN characterization method is proposed, which can simply catch the missing RTN statistics beyond the narrow “detectable window” of VG in conventional DC RTN method, thus is powerful for studying RTN under...
The impact of random telegraph noise on ring oscillator (ROSC) frequency was measured for the first time using an on-chip beat frequency detection system. The proposed differential sensing scheme achieves a high frequency measurement resolution (>0.01%) at a short sampling time (>1µs) allowing efficient collection of RTN induced frequency shifts. Experimental data from a ROSC array fabricated...
Although only a few defects will be present in the gate dielectric of deeply-downscaled CMOS devices, their relative impact may become intolerable [1]. An individual charged defect can significantly alter the channel current ID of a nm-sized FET, causing VTH fluctuations (RTN) and time dependent ΔVTH variability. Based on detailed understanding of atomistic devices, random dopant fluctuation (RDF)...
We report on a novel EWF engineering approach enabling wide VT modulation in aggressively scaled RMG-HKL planar and multi-gate FinFET-based devices with high aspect-ratio gate trenches. Key features include: 1) Al diffusion control from fill-metal (CoxAly) through an ultra-thin TaN layer on HfO2/TiN and fine-tuned TiN/ TaN thicknesses; 2) optimized TiN films for enhanced (NMOS) or inhibited (PMOS)...
A novel Source Drain Extension (SDE) implantation (imp) technique and its CMOS mask flow were developed for scaled FinFETs. An Arsenic (As) heated imp was demonstrated as a superior n-type SDE doping technique for narrow fins. In order to apply the high temperature imp, the CMOS mask flow using an amorphous Carbon (α-C) was developed.
In this paper, for the first time we investigate and report the effective workfunction (eWF) modulation arising from stress memorization technique (SMT) in advanced replacement metal gate (RMG) CMOS technology. Our SMT data show a strong improvement in NFET short channel effect (SCE) besides a typical strain-induced mobility enhancement, suggesting better eWF. Further investigation proves that the...
Metal-insulator-Si (MIS) tunnel contact is studied using ultrathin, non-stoichiometric TiO2−x interlayer on n- and n+ Si. Systematic analysis indicates a record low Schottky barrier height (SBH) of 0.15eV for Ti metal using 10A thick TiO2−x interlayer (TIns). Ti/TiO2−x/n+ Si contact achieves a record low specific contact resistivity (ρc) of 9.1×10−9Ω-cm2.The modeling of ρc suggests tunneling mass,...
In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell...
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed. Introduction Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream [1–4]. They offer unique promise to important circuits such as static RAM cells. Planar fully-depleted devices come in two flavors:...
We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% Iread at Vdd=1V and 0.6V, respectively vs 28LP bulk. Additionally, −100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative...
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVµm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVµm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing...
For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2/Poly-Si:P gate stack and the first electrical...
We systematically study the channel size dependence of 1/f noise and RTN amplitude in nanowire transistors (NW Tr.) by measuring a large number of samples with various parameters such as NW width (WNW), height (HNW), and number (NNW). For a wide range of Lg, WNW and HNW, the universal line appears in the noise (SId/Id2) - 1/(LgWeff) plot explained by conventional carrier number fluctuations. But,...
High-performance strained Silicon-On-Insulator (sSOI) nanowires (NW) with gate width (WNW) and length (LG) scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current (ION=1420µA/µm at IOFF=300nA/µm) and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement...
A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the Ion/Ioff current ratio is 108. The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier...
A synthetic electric field effect to enhance the tunnel FET (TFET) performances is proposed. The TFET utilizes both orthogonal and parallel electric fields induced by a wrapped gate electrode configuration. The device concept was experimentally verified by fabricating Si-TFETs integrated with ultrathin epitaxial channel. Scaling of both the channel width and channel thickness enhances the TFET performance...
We demonstrate on-chip pattern recognition in a neural network circuit using a non-volatile memory for the first time. The synapse chip of the neural network consists of a stack of CMOS circuits and three-terminal ferroelectric memristors (3T-FeMEMs). By using the analog and non-volatile conductance change of the 3T-FeMEM as a synaptic weight, the matrix patterns are learned. Even when an incomplete...
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