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As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar...
While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had...
For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame...
A new charge injection Super-lattice Phase Change Memory was developed with optimized GeTe/Sb2Te3 deposition and state-of-the-art analytical techniques. First principle calculations showed the charge injection enhanced Ge atom movement for the first time. We achieved 0.46 V and 3.3 MA/cm2 reset and MLC programming. The stability of Super-lattice after 1E6 cycles was verified by thermal analysis characteristic...
To improve writing bandwidth for phase change memory (PCM) volume-confined cells are proposed to reduce the reset current [1, 2]. So far, CVD or ALD GST must be used to fill the small hole, with several negative issues. This work proposes and demonstrates a PVD GST volume-confined structure by using an isolation-last process. In our structure, a low aspect ratio (< 1) trench is created and PVD...
We fabricated a new scalable multi-level cell for spin transfer torque magnetoresistive random-access memory that consists of stacked perpendicular magnetic tunnel junctions (MTJs) with a diameter of 50nm using one step etching. The cell features series-connecting MTJs using perpendicular magnetic anisotropy at the CoFeB/MgO interface and a well controlled stray field from the pinned layers resulting...
We propose a new top-pinned perpendicular MTJ structure that can both achieve the magnetic stability of a pinned layer and reduce a magnetic stray-field to a free layer. The key point of the structure is that there is a large design margin of a pin configuration for the stray-field reduction due to a counter bias magnetic field layer being used instead of a SAF structure. Stable switching performances...
We have developed magnetic domain wall (DW) motion cells with a perpendicularly magnetized CoFeB free layer and underlying hard magnets. Low current writing operation of 0.16 mA and a high MR ratio of 80% were attained for the 130-nm-wide free layer. Write/read operation for a 16kb array and high endurance features were also confirmed.
Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future...
Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process for the first time. Here, we obtained not only the improved transconductance (GM) and drain conductance (GD), but also the enlarged operation voltage window employing multi gate oxide structure combined with DWF gate stack. Also, the discriminative...
Time of flight (ToF) sensor with pixel size of 7×7um and VGA resolution is developed using a backside illumination (BSI) structure. Quantum efficiency (QE) of near infrared (NIR) light is improved dramatically by applying thick epitaxial layer, reflection metal and anti-reflection layer. The depth error ranges are 2cm and 10cm at 90% and 10% reflection condition at the distance of 7m, respectively.
A micro-scale mechanical charge pump, cf. Fig. 1(a), comprising a circuit of micromechanical resonant switches (a.k.a., resoswitches) has been demonstrated that generates 3V and 9V from 1V and 3V power supplies, respectively, using a 2-stage design; and 6V from 1V supply using a 5-stage design; all while avoiding the diode voltage drop and breakdown voltage limitations of conventional CMOS-based charge...
We demonstrate a novel p-channel 3D stackable NAND Flash that uses completely new programming and erasing methods. The p-channel 3D NAND avoids the disadvantage of GIDL induced hole erase of floating body n-channel NAND, giving a highly efficient -FN hole erasing and negligible disturb on the SSL and GSL devices. The p-channel NAND structure enables a novel -FN erase selection method, providing a...
A new read method which suppresses the effect of read current fluctuation due to random telegraph noise was proposed to reduce read error in NAND flash memory by using hysteretic characteristic. By controlling the amplitude and polarity of a word-line (WL) bias applied to the gate of a selected cell in a cell string, we can predict stochastically RTN event at μsec time range. From measured transient...
Multi-level cell (MLC) programming is of crucial importance to make a cost competitive NAND Flash product. In conventional 2D floating gate NAND Flash, the interference and disturb become very severe as technology scales, and many methods have been adopted to alleviate the interferences. In 3D NAND, the pitch is generally larger and the charge-trapping device naturally has smaller interference. However,...
3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (tm) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm...
We optimize and investigate extensively the sub-μA bipolar operation of scaled Al2O3- and HfO2-based RRAM cells using carefully thinned dielectrics and Hf scavenging layer. Although isotropic scaling favors the sub-μA operation, switching variability remains intrinsically large due to low number of involved O-vacancy switching species. The low filament temperature also accounts for slow forming/set...
Random telegraph noise (RTN) is a critical reliability metric impacting the memory state during read operation in resistive switching memory. In this study, we develop a time-efficient (a) slow ramped stress technique for quantitative RTN assessment to determine the disturb voltage (VDIST) for oxygen vacancy perturbations in the filament. The technique is used to (b) identify the best regimes of operation...
To satisfy strict requirements of storage-class memory, a bipolar TaOx/TiO2 RRAM has been developed. Numerous highly desired features, including: (1) extremely high endurance over 1012 cycles, (2) forming free, (3) self compliance, (4) self rectification ratio up to 105 required for ultrahigh-density 3D vertical RRAM, (5) multiple-level-per-cell capability, (6) room-temperature process, and (7) fab-friendly...
Ultrathin stoichiometric Ta2O5 layer, which was formed by thermal oxidation of Ta layer on ALD TiO2, exhibits excellent selector characteristics. To maximize the selector performance, we adopted various interface engineering techniques such as Ta2O5 thickness, control of oxygen profile in TaOx layer, top electrode materials, and band gap of bottom insulating oxide layer. By optimizing process conditions,...
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