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On behalf of the organizing committee, we would like to welcome you to the 2013 Symposium on VLSI Technology in Kyoto, June 10–13, 2013, jointly sponsored by the Japan Society of Applied Physics and the IEEE Electron Device Society. The Symposium on VLSI Technology has long been recognized as one of the premiere technical conferences showcasing the latest advancements in semiconductor technology,...
Giga trends in mobile computing, converged devices, cloud, and many other emerging applications continue to drive the growth of Si-based nano-electronics industry. A holistic approach must be taken to meet the demanding system requirements such as energy efficiency, integration density, information throughput, specialty features, and form factor. A new scaling paradigm is proposed, i.e., system scaling,...
During the last few years there has been an explosive growth in demand for smartphones with increasing capabilities and performance. With this demand come many associated hardware challenges.
A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >100µs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process...
We demonstrate for the first time, Si1−xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance...
Highly-strained Ge-in-STI pFETs on SiGe55% SRBs are demonstrated with mobilities up to 550 cm2/Vs and record NBTI reliability at TINV∼1.7 nm. Short channel sGe pFET devices down to 35nm gate length are also reported. This work makes the first use of a germanide in contacts to solve void issues and a high Ge (75%) SiGe S/D for strain enhancement of mobility with an RMG flow providing module learning...
We have developed an image sensor with thin organic photoconductive film (OPF) laminated on CMOS circuits. Owing to high capacity of a charge storage node, the saturation level is 12 dB higher than those of conventional image sensors. Because of the very thinness of the laminated film, i.e. 0.5 µm, the device is crosstalk-free and an incident light angle of over 30 degrees is realized.
It is found that traps inside conduction and valence bands of Ge is the dominating factor of effective mobility reduction for Ge MOSFETs in high Ns region and that surface roughness scattering can quantitatively explain the Hall mobility, which is free from the trapping effects. It is also found that atomic deuterium PDA sufficiently reduces the trap density inside conduction band of Ge, resulting...
We demonstrate a record-high hole mobility ( μeff = 1922 cm2/Vs) of a Ge nanowire MOSFET using Al2O3/GeOx gate stacks having a metal (Schottky) source and drain structure employing doping-free processes. Inserting a plasma-oxide (GeOx) inter-layer between the high-k dielectric and the strained Ge nanowire channel greatly improved not only the mobility but the cut-off characteristics. High intrinsic...
We have fabricated high-quality, high-uniformity GeSn-On-Insulator in a low-temperature process compatible with Si CMOS and BEOL to enable monolithic 3D integration. Excellent interface roughness and electrical passivation are demonstrated.
We report the first demonstration of gate-all-around (GAA) GeSn nanowire (NW) pFETs. The uniaxially compressive strained GeSn NW with a width of 50 nm and a height of 35 nm was fabricated using a CMOS compatible top-down approach. The GeSn GAA NW pFETs with the shortest reported channel length LCH down to 100 nm were realized, and the devices achieve a record high peak intrinsic transconductance G...
Heterogeneous integration of integrated circuits offers an opportunity to create new functionality with tradeoffs between cost, performance, and alternative monolithic integration complexity. We present a study of heterogeneous integration using a large, field programmable gate array (FPGA) research and development vehicle to assess the capabilities of 3D silicon interposer technology. This study...
The exascale computing is required in the Era of Big Data. In order to achieve this demand, new technology innovation must be required and packaging scaling including 3D-IC with TSV (Through Silicon Vias) is one of most promising technology. To increase the total bandwidth, the fine pitch die to die interconnection is necessary. Micro-bumping, thermally enhanced underfill and advanced interposer technologies...
A novel air gap (AG) structure is integrated into TSV formation to achieve high performance interconnects for 3D stacking of 28nm CMOS devices. When benchmarked against conventional TSVs, the most prominent advantages of this novel TSV structure demonstrated reduced capacitance, minimized TSV-induced stress and, hence, reduced keep-out zone (KOZ) for CMOS devices. Our FEM simulation confirms that...
To reduce TSV coupling noise, a new guard-ring technique is proposed and implemented experimentally. We design the n+/n− well guard-ring butted to the TSV dielectric surrounding the TSV and utilize the inversion layer induced by a positive interface charge as a shield layer. The interface trap density responsible for the interface charge between the TSV dielectric and Si substrate was extracted. Proposed...
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art quality factor (Q) = 64 in 2.4GHz inductor has been demonstrated for RF systems. For the first time, radio frequency (RF) circuits with InFO-WLP have been fabricated to illustrate how the high Q inductor can be used to dramatically improve performance and power consumption concurrently.
We report the first demonstration of strained In0.53Ga0.47As-on-insulator (-OI) MOSFETs on Si substrates using the direct wafer bonding (DWB) technique. 1.7 % highly-strained In0.53Ga0.47As-OI structures were successfully fabricated on Si by DWB. Strained In0.53Ga0.47As-OI MOSFETs with Ni-InGaAs metal S/D have successfully operated, for the first time. MOSFETs with 1.7 % tensile strain exhibits 1...
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