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In this paper a CMOS Differential current sensing comparator along with the Buffer stage has been introduced. The simulation is carried out in 130nm and 90nm technologies. The supply voltage for this comparator is 1.3v and 0.9v for 130nm and 90nm respectively. Various analysis of different characteristics of the comparator such as offset, ICMR, propagation delay, power dissipation has been carried...
In this paper analysis of noise margin and power dissipation of a novel low power proposed 8T SRAM cell has been reported. In the proposed structure two voltage sources are connected with the Bit line and the other connected with the Bit bar line are used in order to reduce voltage swings at the output nodes of bit and bit bar line during the write operation. Static noise margin values have been calculated...
As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable...
This work presents the design of a modified two stage operational amplifier in 0.18 μm CMOS technology. The main objective of the design is to make a trade-off between offset voltage and power consumption while maintaining rail-to-rail output swing and high phase margin. For this purpose, transistors with controlled region of operation are included to the output stage. Simulation is done in Cadence...
Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. As power consumption is directly proportional to the dynamic node capacitance, a new...
Operational amplifiers are an integral part of analog and mixed signal design. With the advancement of process technology, the transistor dimensions are rapidly scaling down leading to reduced ro. In deep sub-micron regime, this leads to a fairly small low frequency gain offered by amplifiers. Applications demanding high gain amplifiers suffer at design level. Even multi-stage architectures fail to...
A high gain and low-power down conversion mixer for short range wireless applications is designed in 0.18 μm complementary metal oxide semiconductor (CMOS) technology. During the design, we have adopted current-bleeding technique and a folded Gilbert topology. The mixer is tested at two frequencies e.g., 2.4 GHz and 5.2 GHz. Simulation results revealed that under 1.8 V power supply, the proposed mixer...
This paper presents the design of a high gain low noise amplifier operating in a bandwidth of .5014 GHz for wireless applications. High gain of 16.17dB is achieved at a frequency of 4 GHz. The Low noise amplifier is an electronic amplifier used to amplify possibly very weak signals. Its mostly placed at the front-end of a radio receiver circuit so that the effect of noise from subsequent stages of...
The advantages of simultaneous read and write operations for dual-port SRAM memory cells are well known. In this paper two configurations of dual-port 8-Transistor Differential (8T-D) and 7-Transistor Single End SRAM cells are presented. The benefits of power-delay product and power dissipation are verified. The goals of low power and high performance control of the full CMOS SRAM can be achieved...
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