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Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance...
Reconfigurable system uses bitstream compression to reduce the bitstream size and the memory requirement. The communication bandwidth is improved by reducing the reconfiguration time. Existing research has explored efficient compression with slow decompression or fast decompression at the cost of compression efficiency. This paper proposes a decode-aware compression technique to improve both compression...
In this paper a full subtractor using MTCMOS technique design is proposed. Combinational logic has extensive applications in quantum computing, low power VLSI design and optical computing. Reducing power dissipation is one of the most principle subjects in VLSI design today. But Scaling causes sub threshold leakage currents to become a large component of total power dissipation. Low-power design techniques...
In Wireless sensor networks, existing energy efficient routing algorithms assumed that the sensor nodes are stationary. Some of the applications in WSN must combine with both mobile sensor nodes and fixed sensor nodes in the same networks. When mobility is functioned there should be performance degradation. Because these nodes are equipped with a lesser amount of memory, restricted battery power,...
Asynchronous adiabatic logic (AAL) is a novel low-power design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder cell using double pass transistor with asynchronous adiabatic logic (DPTAAL) is investigated. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces...
As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations. As far as memory applications are concerned the soft errors and single event upsets are always a matter of problem. The paper mainly focuses on the design of an efficient Majority Logic Detector/Decoder...
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
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