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In this paper, we present HCS - Heterogeneous CRAM Scrubbing - for FPGAs. By utilizing stochastic fault modeling for SEUs in CRAM, we present a quantitative estimate of system MTTF improvement through CRAM scrubbing. HCS then leverages the fact that different SEUs have unequal effects on the circuit system operation, and thus the CRAM bits can be scrubbed at different rates based on the sensitivity...
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to soft-error. To improve circuit dependability, various dependable design techniques have been studied. By the same token, evaluation techniques are required to ensure dependability. The most popular evaluation technique is reconfiguration-based fault-injection (FI) analysis. However, most FI analyses are inadequate for the evaluation...
In recent years the number of deployed embedded systems increased significantly. These system-on-chips are widely used for high-availability as well as security applications. Therefore, the reliable operation of these devices plays a vital role and disturbed operation can lead to loss of confidence and trust. To ensure correct operation during random or intentional fault events, injection techniques...
In this work, we have developed a fault-tolerant architecture which is compatible with existing island-style routing network. Due to this compatibility, the proposed architecture can not only be implemented easily in the existing FPGA devices but a new fault-tolerant FPGA device can also be fabricated without refining the existing routing architecture. A generic fault-tolerant Computation Cell is...
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