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Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc‥ An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator,...
In this paper, a new tapered silicon-embedded coreless power inductor is proposed and demonstrated. The width and depth for the different turns of the inductor are designed with different values to reduce the proximity effect. An 18.6 nH inductance and a peak Q factor of 12.1 are achieved at 23 MHz within a chip area of 0.8 mm2. The AC power loss of the inductor is reduced by a maximum of 56% using...
Photovoltaic (PV) installations suffer from a disproportional decrease in output power in case irradiance differences are present in the system. The Delta converter improves the output power in such cases by routing current differences around the shaded substring or module. This paper presents a driver IC for the Delta converter that simultaneously reduces its cost and improves its reliability. The...
An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M1), an avalanche diode (Dav), and poly-crystalline Zener diodes (ZD) and resistor (Rpoly). Mix-mode transient simulations with MEDICI have proven the functionalities of...
Failure during reverse recovery of an IC power diode is examined. It is shown how one-dimensional diode behavior together with mixed-mode tcad can be used to predict safe operating conditions for the actual two-dimensional case.
We report here a study on a monolithic buck converter power IC with on-chip ferrite core inductors. The power IC is designed and fabricated with a standard 0.18µm CMOS process. On-chip inductor with ferrite core is used as the filter inductor in the buck converter. A 0.6–1.2W prototype system in package (SiP) buck converter is designed to operate at frequencies up to 10MHz.
The isolated direct gate driver with Drive-by-Microwave technologies can directly drive a power switching device by wireless power transmission of RF modulated signal through the electromagnetic resonant coupler and requires no additional isolated voltage source. In order to improve the performance such as a fall time characteristic and a power consumption of the gate driver, a new direct gate driver...
The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding...
Aluminium wirebond-less power module structure was investigated and presented in ISPSD 2011 [1]. The features of this structure are high-density packaging with Copper pins connection and power circuit board, low thermal resistance with thick Copper block on Silicon Nitride ceramic substrate and high reliability with epoxy resin moulding. This paper introduces Silicon Carbide MOSFET power module with...
A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1–5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.
This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in...
In this paper, a planar silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) with a 0.3 µm ultra-shallow heavily doped p-body region is presented. The ultra-shallow body provides a much reduced parasitic JFET resistance, resulting in a low specific on-resistance of 18 mΩ·mm2 for a planar device. At the same time, no punch-through problem is caused by the ultra-shallow body, and...
This paper presents different methodologies to optimize devices of smart power technologies for robustness consideration. A split gate concept is used to improve the flatness of Id-Vd curves of the nVDMOS by maintaining the Intrinsic MOS in a stable operating regime. The split gate is also used to increase the BVdss of the pLDMOS. An additional buffer at the end of the drift region of the nLDMOS helps...
This paper discusses a circuit simulation model for interdigitated source LDMOS. As p+ well contacts are inserted to the source regions, the device achieves high breakdown immunity without using high voltage p+ implantation under the source. However, since the parasitic resistance near the source p+ region is not formulated in the conventional compact model, the accuracy of the model is an issue....
A novel Buried Layer Rectifier (BLR) is proposed and demonstrated, which features P-layers buried under the N-channel to create a barrier for majority carriers whose height can be modulated by the anode voltage. The forward conduction voltage (VF) is considerably reduced due to the ultra-low barrier. The buried P-layers also significantly enhance the blocking capability and reduce the leakage current...
The purpose of this study is to clarify the more reliable design for ONO Gate insulator film for Trench Gate MOSFET. Partially Thick Oxide Trench Gate MOSFET (PTOx-TMOS) with ONO Gate film can reduce the Ron*Qgd Figure of Merit on easy process and simple structure. However this structure is required the appropriate design to prevent threshold voltage shift originated in charge storage effect. In this...
In this paper we present a mechanism leading to early fails in a trench power MOSFET when operated at high drain currents under repetitive avalanche conditions (also referred to as “unclamped inductive switching”). While typical fails show burn marks at (or under) the bond stitches, early fails can occur close to the active area's edges or corners. With plausible assumptions both cases can be consistently...
In this study, a reduction in the saturation current caused by self-heating effect at high VGS is observed in a 35-V rated asymmetric DEMOSFET. The high VGS -induced the large current and raises up the device surface temperature. The Kirk-effect takes places at sufficiently high current levels (high VGS values) leading to the movement of the maximum temperature point from the gate-overlapped DE (drain-extended)...
In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and...
a 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 µm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate...
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