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As future microprocessors will be prone to various types of errors, researchers have looked into cross-layer hardware-software reliability solutions to reduce overheads. These mechanisms are shown to be effective when evaluated with statistical fault injection (SFI). However, under SFI, a large number of injected faults can be derated, making the evaluation less rigorous. To handle this problem, we...
Modern microprocessors have many micro architectural features. Quantifying the performance impact of one feature such as dynamic branch prediction can be difficult. On one hand, a timing simulator can predict the difference in performance given two different implementations of the technique, but simulators can be quite inaccurate. On the other hand, real systems are very accurate representations of...
While a canonical out-of-order engine can effectively exploit implicit parallelism in sequential programs, its effectiveness is often hindered by instruction and data supply imperfections manifested as branch mispredictions and cache misses. Accurate and deep look-ahead guided by a slice of the executed program is a simple yet effective approach to mitigate the performance impact of branch mispredictions...
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