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A fully differential (FD) voltage buffer suited to low-voltage operation and able to operate over a wide voltage range is presented. The buffer core is based on a FD difference amplifier including bulk-driven MOS transistors as input devices. The common-mode (CM) component of the buffer output voltage is controlled by means of a bulk-driven CM feedback (CMFB) network that features an extended operating...
A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed...
An analog cochlear implant topology realized by utilizing the concept of Sinh-Domain filtering is presented in this work. Owing to the inherent class-AB operation of Sinh-Domain filters, the proposed topology has the capability for handling currents larger than the corresponding dc bias currents, and avoiding the employment of two identical signal paths constructed from class-A configurations, as...
In this paper a new current-mode precision full-wave rectifier using is presented. It uses only single dual-X second generation current conveyor and two diodes. The main advantage of the proposed circuit is the high-impedance output, hence, by appropriate loading, voltage response can also be obtained. Using the CMOS implementation of the active element, the performance of the rectifier is analyzed...
In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.
In this paper, the impact of the NMOS/PMOS imbalance on Ultra-Low Voltage (ULV) circuits and their design is discussed within a unitary framework for the first time. Variations are shown to dramatically affect imbalance due to the long-tailed probability density and high variability. The impact of the imbalance on the minimum supply voltage VDD,min ensuring correct gate switching is studied analytically...
The Fibonacci Switched-Capacitor (SC) converter demonstrates the highest performance by using minimum number of capacitors. However, as the Fibonacci SC requires a wide range of voltage rating of the devices, its implementation is difficult. This paper presents two gate driving techniques for designing and implementing two-phase Fibonacci SC converter for both low and high step-up conversion ratios...
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