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In this paper we present a complete study on the balance between high performance image processing and low power consumption without using expensive components. Our proposal consists in implementing a Discrete Time Cellular Neural Network (DT-CNN) on a low power Actel IGLOO nano Field Programmable Gate Array (FPGA). This is a definitive step further from previous work to obtain an intelligent camera...
Ring Imaging Cherenkov detectors (RICH) are a class of particle detectors used for particle identification whose principle involves a pattern recognition problem: identifying circles from a short number of their points. A real image hosts several circles which may eventually overlap. Actual techniques solving this problem are mainly non-local algorithms implemented on software requiring large computing...
This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ−Δ) Modulator to measure and assess its performance. The CT Σ−Δ modulator/decimation filter cascade...
This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to implement the lattice approach can be obtained by an off-line preprocessing that can be automated. Other advantages of the proposal are that it implements a continuous PWA function...
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should...
The paper presents a package of arithmetic operation synthesis dedicated to reconfigurable logic controllers programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation...
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