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Cognitive radio has been put forward to make efficient use of scarce radio frequency spectrum. Spectrum sensing is the cornerstone of cognitive radio. As a part of the effort toward building a cognitive radio network testbed, we have demonstrated real-time spectrum sensing. However, current hardware platforms for cognitive radio introduce time delays that actually undermine the accuracy of spectrum...
This paper reports a research testbed of real-time ultra-wideband (UWB) multiple-input multiple-output (MIMO) radio. In the receiver design, the UWB MIMO receiver supports up to eight channels, where each channel is equipped with an analog-to-digital converter (ADC) with 8-bit resolution and sampling rate up to 3 Giga samples per second (Gsps). The transmitter is able to transmit two independent arbitrary...
As a result the exponentially increased power consumption of IC chips, how to deal with the heat generated by processors has become a major concern in design of computing systems. Recently, we have seen extensive theoretical research results on dynamic thermal aware computing published in the literature. However, there are not many experimental researches reported based on practical computing platforms...
Cognitive radio has been put forward to make efficient use of scarce radio frequency spectrum. A testbed for cognitive radio can not only verify concepts, algorithms, and protocols, but also dig out more practical problems for future research. However, to our best knowledge, an authentic real-time cognitive radio system has never been demonstrated. In order to build a cognitive radio network testbed,...
The purpose of this paper is to identify the advantages of including a floating point hardware / a mathematical co-processor in microcontrollers used for critical floating point operations. Three different microcontrollers are considered: Renesas M16C/62P (CISC without FPU), ATMEGA1280 (RISC without MCU) and Renesas RX62N (CISC with FPU). Gauss-Seidel and Jacobi iterations for a system of 2 and 3...
This paper presents the design and implementation of a hardware graphical display custom processor for generating and manipulating plots based on a given set of time varying input signals. The paper primarily focuses on the design to generate plots of two sampled sine waves of 5 KHz and 10 KHz respectively, along with horizontal and vertical axes with proper scaling. This was achieved by designing...
Robotic simulators, frameworks, and related toolkits are very important in today's research community. The need to accurately simulate movements, algorithms, and interactions with the real world is quickly becoming a major research focus as humans and robots interact in more situations and differently than ever before. This is a survey of popular robotics simulators and some of the main frameworks...
This paper discusses generation of test vectors for digital components from their VHDL behavioral models, prior to synthesis into specific gate level implementations. This allows test planning to proceed in parallel with the development process, rather than waiting until the design is complete. The test vectors are generated from behavioral fault models based on generalized functional faults that...
The eikonal partial differential equation is solved using a modified level set algorithm which is then transformed into a proposed field programmable gate array implementation. The numerical method for isotropic material eikonal hardware engines is extended to angle dependent anisotropic media in two dimensions. This new method transforms the eigenvalue iteration into a process which executes in constant...
One of the newest computational technologies is the high performance heterogeneous computer (HPHC) wherein dissimilar computational devices such as general purpose processors, graphics processors, field programmable gate arrays (FPGAs), etc., are used within a single platform to obtain a computational speedup. Jackson State University has a state-of-art HPHC cluster (an SRC-7), which contains traditional...
Finding the behavior of application programs has been studied by many researchers to improve the performance. Especially, reuse distance, number of distinct data element between two adjacent references to a data element, has been studied by many researchers since reuse distance is independent of hardware architecture configurations. However, with the advent of multicore architectures, predicting the...
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