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An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected...
This paper examines the feasibility of utilizing a 2-dimensional (2-D) mesh of run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA for throughput- and real-time-driven tasks. To utilize a 2-D mesh of RTRMs, efficient communication architectures (CA) are required, which will be presented in this work. Such a 2-D mesh of RTRMs on a DPR-capable FPGA can be...
The paper analyzes and proposes some enhancements of Ring Oscillator based Physical Unclonable Functions (PUFs) that are used to extract a unique signature of an integrated circuit in order to be used for device authentication purposes and/or key generation. We analyze in more details the concept developed by Suh et al. in 2007. Contrary to what authors claim, we show that the designer of the Ring...
We propose in this paper a hybrid router architecture which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffics generated in real-time applications. The SDM approach is used in circuit switching in order to increase path diversity, thus improving throughput while mitigating the...
We propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floor planning, routers assignment, and routing paths calculation steps. The proposed heuristic methodology integrates fast algorithms based on the B*-tree representation for floor planning, on bipartite matching for the routers assignment step, and on multi commodity flow for congestion minimization for the...
Reconfigurable systems have been shown to achieve very high performance. However, the overhead associated with reconfiguration of hardware remains a critical factor in overall system performance. This paper discusses the development and evaluation of a technique to minimize the delay associated with reconfiguration based upon optimized sharing of configuration bit streams between design contexts....
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