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SRAM based fingerprinting is a promising technique for unique identification of physical devices. This method uses deviations in power-up behaviour caused by the CMOS fabrication process to identify physical devices. In the case of SRAM-based hardware reconfigurable devices such as FPGAs the integrated SRAM cells are often initialized automatically at power-up, sweeping potential identification data...
This paper presents the design and analysis of an area efficient implementation of the SHA-3 candidate Blue Midnight Wish (BMW-256) hash function with digest size of 256 bits on an FPGA platform. Our architecture is based on a 32 bit data-path. The core functionality with finalization implementation without padding stage of BMW on Xilinx Virtex-5 FPGA requires 84 slices and two blocks of memory: one...
This paper presents the mapping of an object detection application for aerial image based vehicle detection on highways onto a configurable heterogeneous RISC/coprocessor architecture. An extended pipelined processing scheme exploits the coprocessor features for parallel task processing. An alternative latency minimized processing scheme removes data dependencies in the application and improves parallel...
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