The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this work, a deep submicron double-gate (DG) Gallium Nitride (GaN)-MESFET design and its 2-D threshold analytical model have been proposed and expected to suppress the short-channel-effects for deep submicron GaN-MESFET-based low power applications. The model predicts that the threshold voltage is greatly improved in comparison with the conventional Single-Gate GaN-MESFET. The developed approaches...
This paper presents an extended CAD tool compatible with decananometric technologies for sizing OTA architectures. This is based on an extension of the gm/I methodology which uses, as inputs, parameters directly extracted from foundry models and can hence be easily ported to different technologies. This tool was developed in order to fasten and automate design for each OTA architecture. From fixed...
We present the calculation of noise expressions of low voltage amplifiers by applying symbolic nodal analysis and using nullors. The nullor equivalents of the MOSFETs include only the dominant parasitic elements in order to generate a simplified symbolic noise expression, which provides a good insight to improve the design of low voltage amplifiers. The generated symbolic noise expressions are compared...
In this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35μm process parameters. Using the proposed...
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD.
In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.