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This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated for the...
This paper presents an extended CAD tool compatible with decananometric technologies for sizing OTA architectures. This is based on an extension of the gm/I methodology which uses, as inputs, parameters directly extracted from foundry models and can hence be easily ported to different technologies. This tool was developed in order to fasten and automate design for each OTA architecture. From fixed...
In complementary input differential pair circuits, the topology CMOS uses both an nMOS differential pair and a pMOS differential pair connected in parallel however, it produces variations in the transconductance over the input common mode range. To avoid the problem of transconductance variations, a new structure, consists of two op-amps one n-type and the other p-type controlled by a digital control...
In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation...
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD.
In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results...
New analytical equations are proposed for oscillation amplitude of the MOS Colpitts oscillator. These equations are obtained from a large signal analysis. The analysis is based on a reasonable estimation for the output waveform. The estimated waveform should satisfy the nonlinear differential equations governing the circuit. The validity of the resulted equations is verified through simulations using...
Particle swarm optimization (PSO) has shown to be an efficient, robust and simple optimization algorithm. Recently, the mono-objective version of the PSO algorithm was adapted and used to optimize only one performance of RF circuits, mainly the voltage gain of low noise amplifiers. In this work, we propose to optimize more than one performance function of LNAs while satisfying imposed and inherent...
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