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With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
This paper proposes a novel multi-core processor with SIMD(Single Instruction Multiple Data) ISA (Instruction Set Architecture) and extended register file for communication applications. To acquire better parallel computing capability, we implement SIMD ISA and increase the number of register file from 32 to 64. 5×5 homogeneous 2-D mesh NoC (Network-on-Chip) topology is adopted to further enhance...
With the amount of calculation for wireless and multi-media applications increasing, the Multi-Processor System-on-a-Chip (MPSoC) based on Network-on-Chip (NoC) is used to process massive data in a distributed fashion. Compared with heterogeneous architecture for general embedded low power DSP, homogeneous NoC architecture is much more flexible for dynamical task assignment. In this paper, a new NoC...
With increasing scale of Network-on-Chips (NoCs), the power caused by long line wires between cores counts for a significant proportion of the NoCs energy consumption. Most of the study on NoCs topologies assume that interconnect wires between cores are same length and are short lines. Taking 2D 4×4 torus network as an example in this paper, we present a long line interconnects network model for analyzing...
A small-granularity solution with high performance and low area cost for fault-tolerant routing of hard error in 2D-Mesh Network-on-Chip is proposed. This solution presents a new fault model, defines separately node-fault and link-fault, reduces situations classified as node-fault effectively, and consequently improves the performance of the network. By defining some new paths to substitute failure...
This paper presents a reconfigurable data protection controller (DPC) so as to eliminate the security threats against network-on-chip (NoC) system. The proposed DPC can terminate the illegal accesses to the shared-memory of NoC system before the links to target location have been established, thus greatly save link resource and energy. Moreover, according to the implementation results based on SMIC...
A data frame synchronization sequence processor in HiNoC receiver is implemented in this paper. It is the important module for channel estimation and channel correction. 63-point FFT, phase extracting method and so on are presented considering hardware resource. The design has been fabricated with SMIC 0.13um technology.
Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail,...
Among current outstanding research problems in NoC Design, mapping application onto NoC is one of the core issues to be explored. In this paper, we propose two methods for mapping a pip elined flow chart onto mesh-based NoC system: Communication Length Concerned (CLC) method and Space Restricted (SR) method after a simple pre-process. The former significantly reduces the latency and energy consumption...
Network-on-Chip (NoC) has been proposed as a paradigm for the network, wireless and multimedia applications executing on embedded chips with massive data processing. It requires high speed data transferring and low power consumption, and then efficient and accurate performance estimation tools are needed for system level optimization and analysis in a flexible way. In this paper, a new NoC simulator...
Network-on-Chip (NoC) is the most promising on-chip-interconnection scheme for multi-core processors. In this paper, we propose a novel NoC architecture called Stargon, which is inspired by the Spidergon. A simulation model has been developed to evaluate our architecture. We study the effect of the number of nodes, buffer depth and message length on the performance, and shows that at any situation...
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