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This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
Stability is a critical design issue for radiation detection readout circuit when high counting rate together with low power property is simultaneously required. In this letter a novel method which increases the phase margin of the pulse shaper is presented. A readout circuit using this compensation technique has been implemented in 0.35 μ CMOS technology. Simulation and test results show that this...
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
ADC is one of the key components employed in the digital controlled DC-DC converters. In this paper, a low power and high resolution algorithmic ADC is designed, which is suitable to the integrated digital controllers for high-frequency and low-power switched DC-DC converter. The designed 8-bit algorithmic ADC has 2 bits per stage. Simulation results show that ENOB up to 7.6bit is obtained. As one...
A CMOS capacitor-free low-dropout (LDO) voltage regulator with 0.65-1.8 V power supply is presented. Positive feedback is used to build the differential computation of the error amplifier and the positive feedback gain is less than unity to ensure the stability. The LDO is designed in TSMC 0.18 μm CMOS processes. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The simulation...
This paper describes a novel bandgap reference with high PSRR over a wide frequency range. The design utilizes an internally regulated supply voltage without high gain feedback loop. Thus improve PSRR even at high frequency. Additional transistors are added to further improve supply rejection and minimize the second order effect. The circuit is implemented in 0.25 μm CMOS technology. It generates...
This paper described a digitally controlled Buck converter. In this converter, the compensator implements the classic linear PID control law by the fixed-point algorithm. A proposed verification method is performed in Simulink environment. The structure of low area and power cost Ring ADC and high resolution DPWM is also introduced, respectively. The consistent mathematic and Spice simulation result...
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
This paper presents the low-power implementation of a 10-bit 150-MS/s pipelined analog-to-digital converter (ADC) in a standard 65 nm digital CMOS. The ADC removes the track-and-hold amplifier (THA) to reduce the power consumption. A 1.5 bit/stage architecture is used in the first stage to lower front-end design complexity. Three 2.5-bit stages are followed to reduce the stage number in the pipeline...
A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
This paper introduces an approach for the design of an adaptive non-linear digital Fuzzy logic controller for a digital controlled auto-adjustable Buck DC-DC converter, which is validated by Simulink tools of Matlab. The setup time of the output voltage was about 10μs and the steady state error was less than 2mV with the proposed controller. When the supply voltage or load current was disturbed, the...
In this paper, an advanced charge pump optimization methodology based on DOE technique is proposed. Compared with other optimization methods, this methodology constructs accurate mathematical models between the outputs and the input parameters with a few simulations through response surface technique and regression analysis. Moreover, owing to the simplification of the number of main charge pump input...
In this paper, the detailed design procedure for two operational amplifiers (OP-Amp) used in charge pumps (CP) is presented. Such procedure, which is from system-level specifications to circuit-level requirements, provides a general methodology for OP-Amp design in CP. The design was simulated in a 0.18μm CMOS process and occupies a layout area of about 200μm×100μm. The simulation results show that...
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate...
A white LED driver chip applied in backlight is proposed, which is based on pulse width modulator. The design of modules such as current reference, oscillator and dynamic slope compensation are discussed in detail. The simulation results, based on CSMC 0.5μm BCD technology, show that the input voltage is in the range of 3.3~5.5V, the output voltage is up to 20V when the output current is between 15...
This paper designs a 10th order switched-capacitor (SC) band-pass filter and its 6th order active-RC low-pass smooth filter. The center frequency and -3dB pass bandwidth of the SC filter are respectively 50kHz and 10kHz. The filters are used in a low-frequency communication system. At low frequency, the MOSFETs have large flicker noise. This paper designs an optimized low noise full differential op...
A switch-mode Li-ion battery charger is proposed. It is suitable for input power supply of wall adaptor or USB port in modern portable apparatus. When it works under USB port supply, its input current is automatically limited at a presetting value. A power-path management is introduced in to realize charging and power supply simultaneously based on load priority. It also realizes smooth transition...
A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current...
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