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The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
We have developed a new thermal CVD technique for poly-SiGe thin films that meets the requirements for low-cost fabrication of post-amorphous silicon (a-Si:H) TFTs, i.e., Reactive Thermal CVD featuring a set of reactive source materials of disilane (Si2H6) and germanium tetrafluoride (GeF4). We succeeded in deposition of poly-SiGe thin films at 450°C or higher on glass substrates by this technique...
The edge field enhanced deep depletion phenomenon in metal-oxide-semiconductor (MOS) structure was demonstrated. The analysis in inversion to deep depletion of ultra-thin SiO2 and HfO2 was conducted using critical field model. By examine the field ratio between edge and bulk, it is observed that the HfO2 has larger ratio than SiO2. It is supposed the edge field enhanced deep depletion phenomenon dominates...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
We have investigated the role of oxygen in Hf-based high-k gate stacks on Vfb shift. It is clearly shown that the Vfb of the HfSiOx-based high-k materials of the weak ionic oxide was almost constant irrespective of the oxidation annealing temperature. On the other hand, the HfO2-based high-k materials of the strong ionic oxide caused the positive Vfb shifts by introducing additional oxygen into high-k...
As the scaling of transistors proceeds towards the deep sub-micron level, there is a need of replacement of intermetal dielectric (IMD) from SiO2 (k = 4.2) to a material with dielectric constant k <; 3. In this study, we choose porous SiCOH with dielectric constant k = 2.4 for the use as IMD layer. The quantitative analysis of the elements present in SiCOH has been performed by electron energy-loss...
This is the first report of a technique for inserting a thin Zr interlayer into a nickel film to improve the thermal stability of the silicide formed from this film. The sheet resistance of resulting Ni(Zr)Si film was lower than 2 Ω/□. X-ray diffraction and raman spectral analysis showed that only the silicides low resistance phase (NiSi), rather than high resistance phase (NiSi2), was present in...
We have proposed atomistic guiding principles for high program/erase (P/E) cycle endurance MONOS type memories based on first principles calculations. We found that excess O atoms near the SiN/SiO2 interfaces are the cause of memory degradation due to an irreversible structural change during P/E cycles. These results indicate that by suppressing excess O atoms the MONOS characteristics can be effectively...
We compare the switching behavior of two classes of resistive RAMs (RRAMs), namely Cu-SiO2 based conductive-bridging-RAMS (CBRAMs) and HfO2 based Oxide-RRAMs (OxRRAMs). In both devices the ON/OFF ratios are high, the set voltage is reproducible from cycle to cycle, and the reset voltage displays large dispersion. No forming stage is required in the investigated OxRRAMs. CBRAMs offer much lower programming...
SiNx-doped Sb2Te3 films for nonvolatile memories were prepared by co-sputtering with Si3N4 and Sb2Te3 alloy targets. Electrical and structural properties were investigated and compared to those of conventional GST and pure Sb2Te3 film by annealing temperature-dependent resistivity measurement, x-ray diffraction (XRD). The resistivity ratio is larger than 105 during the phase transition, accompanied...
Two topics are introduced from our studies on the formation mechanisms of nanochannels: thermal silicon oxidation to form silicon wire channels, and silicon-carbide thermal decomposition to form atomically thin graphene channels. Silicon emission and oxide viscous flow processes are necessary to explain thermal oxidation to form silicon nanochannels. Interfacial growth should be considered for the...
In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering...
A novel structure of 4H-SiC MESFETs is proposed which focuses on surface trap suppression. A MOS gate controlled spacer layer is shown to improve both DC and AC characteristics due to suppressed surface effect and decreased gate capacitance. A very high power density of 6.1 W/mm is obtained at S band operation. Compare with the well recognized buried gate structure, there is a significant improvement...
Shaped nanomembranes offer huge potential for integration of novel devices and device concepts on a single chip. We show that strained nanomembranes can form into long-range-ordered wrinkled patterns on rigid and soft substrates, which is exploited to create nanofluidic channel systems and stretchable/flexible magnetoelectronic devices. Nanomembranes can also roll-up into tubular geometries, offering...
TaN was widely used as Cu diffusion barrier in CMOS Cu-BEOL technology, in which it was removed by CMP process. Some work was done on TaN etch by Br/Cl-based gas for metal gate application. But seldom work was done for TaN etch in CF-based gas. In this work TaN etching in CF4/CHF3 gas was investigated on CVD alpha-Si substrate for CMOS compatible MEMS/Sensor application. To avoid resist poisoning...
Three types of defects, namely comet I, comet II and carrot, in thick 4H-SiC homoepilayer were investigated by the micro-Raman scattering measurements. Comet defects were originated from certain cores which caused by the point defects or the inclusions on the surface of the substrate. 3C-SiC inclusions, which were not contained in carrot, were found in comet defects. The different distribution of...
Normalized Differential Conductance Spectroscopy (NDCS) has been used to investigate the tunneling properties of post soft breakdown SiO2. It is shown that the NDCS is capable of separating various components of tunneling current and determining its corresponding tunnel constants of post SBD SiO2. Therefore, the most important tunneling parameters: the effective mass of tunneling electron in SBD SiO...
Cubic silicon carbide (3C-SiC) has received a great deal of attention since it is a suitable material for electronic and MEMS devices operating in harsh environments. But difficulties still exist in realizing high throughput of high quality material. In the present paper, 3C-SiC layers have been grown on Si(111) in a vertical multi-wafer WCVD (Warm-wall Chemical Vapor Deposition) reactor with a rotating...
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