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A Constant-gm CMOS op-amp with Rail-to-Rail input and output stage is proposed in this paper. It is based on a novel configuration that consists of four MOSFETS as dummy differential pairs to select different differential pair as input pair, according to the different common-mode voltage. The constant gm is accomplished by avoiding the input NMOS and PMOS differential pairs operating synchronously,...
Although audio-band sigma delta ADC has largely been implemented as discrete time circuits, a continuous time approach offers significant advantages for high accuracy low-power applications. A continuous time design allows for relaxed amplifier unity-gain bandwidth and power requirements. It also provides better noise immunity due to their inherent anti-aliasing properties. This paper introduces a...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
This paper presents a high gain and wide bandwidth fully differential operational amplifier (op amp) used in a sample and hold amplifier (SHA) circuit for a 12bit, 50Ms/s pipelined ADC. The gain-boosted technique is adopted to achieve a high gain without reduction of the output swing, while a new frequency compensation method is developed to compensate the bandwidth degradation caused by the gain-boosted...
This paper presents a technique to sense and amplify small differential signal with tunable gain from 10 to 100. This amplifier can work with wide common mode input voltage ranges from -7 V to 90 V. One offset cancellation block is introduced, in order to realize system self-calibration which is possible to reduce equivalent input offset voltage to less than 0.5 mV.
The paper describes the design and implementation of a speaker driver applied to Class G/Class I with single phase power supply. Gain expanding and compressing technology are employed in signal processing circuit to optimize power dissipation. Experimental results using 0.18μm N-well CMOS show that it can obtain less than 0.006% THD at low power range and less than 0.4% at medium power range with...
This paper presents a 12-bit 5MS/s pipeline analog-to-digital converter implemented in a 0.5μm CMOS technology for aerospace extreme environment applications with cryogenic and radiation tolerant capability. It is capable of working under ultra-wide temperature range from -180°C to +120°C and at ultra low temperature of -230°C. To achieve higher sampling rate and lower power, time-interleaved architecture...
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance...
The problem of slow convergence speed exists in the correlation-based digital background calibration techniques for the pipeline ADC. The proposed improved techniques reduce the signal-dependent interference amplitude by clipping MSBs off the ADC output. Meanwhile, the exponential averager is introduced into the LMS iteration. These means can not only calibrate capacitors mismatch in MDACs and the...
A 4th order Chebyshev complex filter with stop band zeros at the DC point for low-IF receivers' applications using 0.18μm CMOS technology is proposed in this paper. Based on capacitor-OTA integrators, the designed ladder filter uses resistors instead of capacitors to realize the transmission zeros. The complex filter has a 0 to 48dB tunable gain (6dB per step) and over 65dB DC-offset rejection. A...
This paper presents the low-power implementation of a 10-bit 150-MS/s pipelined analog-to-digital converter (ADC) in a standard 65 nm digital CMOS. The ADC removes the track-and-hold amplifier (THA) to reduce the power consumption. A 1.5 bit/stage architecture is used in the first stage to lower front-end design complexity. Three 2.5-bit stages are followed to reduce the stage number in the pipeline...
A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
In this paper, the detailed design procedure for two operational amplifiers (OP-Amp) used in charge pumps (CP) is presented. Such procedure, which is from system-level specifications to circuit-level requirements, provides a general methodology for OP-Amp design in CP. The design was simulated in a 0.18μm CMOS process and occupies a layout area of about 200μm×100μm. The simulation results show that...
An analog baseband circuitry for a China Mobile Multimedia Broadcasting (CMMB) direct conversion tuner IC is introduced in this paper. It includes an 8th order channel select filter with sharp transition band and utilizes a novel gain-bandwidth-product (GBW) extension technique in designing the low power, high speed operational amplifiers (Op-Amps) of the active-RC filter. A current steering type...
Based on Brokaw bandgap cell, an improved implementation of BGR which consists of a temperature compensated circuit and a simple feedback loop circuit is presented. The circuit exploits a high-order compensation method to realize a low TC and uses an op-amp-avoided feedback loop circuit to save the power dissipation. Implemented in 0.5μm BCD process, the proposed circuit achieves a TC of 1.9 ppm/°C...
Output setting time of operational amplifier consists of output large-signal setting time and output small-signal setting time. In order to increase the output setting time, it is necessary to increase both the slew rate and the gain-bandwidth product at the same time. In this paper, an operational amplifier structure is designed which can increase SR and GBW. The GBW of the whole operational amplifier...
This paper designs a 10th order switched-capacitor (SC) band-pass filter and its 6th order active-RC low-pass smooth filter. The center frequency and -3dB pass bandwidth of the SC filter are respectively 50kHz and 10kHz. The filters are used in a low-frequency communication system. At low frequency, the MOSFETs have large flicker noise. This paper designs an optimized low noise full differential op...
In this paper, a 4-channel photocurrent detector is described which is used in the field of photoelectric detection. Each channel of the detector consists of TIAs and voltage comparator, and current detection threshold can be set by external voltage. The TIA has measured 1.5mA input current overload capacity and 1.9 nArms equivalent input noise current level. The detector is processed in 2 um all-NPN...
This paper presents a 12-bit 50-MS/s pipelined Analog-to-Digital Converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid architecture is selected to make a trade-off between the power dissipation and performance of the ADC. For subsampling application, a wideband Sample and Hold Circuit (SHC) is proposed, including a high-linearity input switch and a two-stage operational amplifier (opamp) with hybrid...
This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs...
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