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This paper presents highly-efficient RF polar transmitter (TX) systems that utilize the envelope-tacking (ET) technique with monolithic SiGe power amplifiers (PAs) for mobile WiMAX and 3GPP Long Term Evolution (LTE) applications. Monolithic single-ended cascode SiGe PA design capable of enhancing its power-added efficiency (PAE) is demonstrated. Four RF switches are adopted at the bases of the common-emitter...
A low-power high-linearity PGA (Programmable Gain Amplifier) is proposed in this paper. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. This PGA is fabricated in TSMC 0.13um CMOS technology. The measurements show that the PGA provides 64dB (3dB~66dB) gain range with a step of 1dB, the...
In this paper, a 14-bit low power self-timed differential SAR ADC with a new structure high precision multi-segment bandgap reference (BGR) is presented. In this design, Self-timed bit-cycling is adopted to enhance the time efficiency. Gray coding form mode control words are utilized instead of binary for mode control to reduce substrate noise and enhance the linearity of the whole system.
In this paper, we designed a 1.2-V low supply voltage transconductance-C (Gm-C) low pass filter (LPF) for transmitter analog baseband front-end of wireless local area network (WLAN) transceiver applications. The filter's cut-off frequency is 10MHz and PIIP3 is 8.4dBm. The LPF uses a 3rd-order Chebyshev prototype. The filter is fabricated in TSMC 0.13-μm CMOS technology and drains 3.8mA from a 1.2-V...
A third order Gm-C reconfigurable Butterworth low-pass filter for SDR receivers with a tunable cutoff frequency of 5M to 50M is presented. A positive feed-forward compensation Gm-cell is utilized to improve the linearity of the filter. The filter has been implemented in SMIC 130nm CMOS process. It occupies 0.63 mm2 die area and consumers 12mA - 16mA current with a 1.2V power supply. The measured in-band...
This paper discusses the design and implementation of a sample-and-hold circuit integrated into a high-speed and high-resolution A/D converter. In order to achieve the required speed and resolution, mixed MOS transistor channel length amplifier is used. The sample-and-hold circuit processes a differential 2.5-Vp-p output signal swing and achieves 16-bit linearity with sampling frequency up to 100...
A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
An analog baseband circuitry for a China Mobile Multimedia Broadcasting (CMMB) direct conversion tuner IC is introduced in this paper. It includes an 8th order channel select filter with sharp transition band and utilizes a novel gain-bandwidth-product (GBW) extension technique in designing the low power, high speed operational amplifiers (Op-Amps) of the active-RC filter. A current steering type...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
A 1.2V Gilbert mixer with improved linearity and noise figure is presented. To improve the linearity, an optimum gate bias is applied to the transconductance stage, and a series LC network resonating around 2fLO is implemented at the common source nodes of the switch quad. Analysis shows that the flicker noise performance also benefits from the series resonating network. The 2.1GHz mixer fabricated...
A highly integrated 0.13um CMOS direct conversion transmitter front-end for wide-band code division multiple access (WCDMA) is presented. The transmitter delivers +6.8dBm output power while consuming 39mA. The overall gain can be programmed in 6dB steps over a 66dB range with 0.1dB accuracy. The transmitter front-end achieves an OIP3 with +19.2dBm, an error vector magnitude of 3.7%, and an adjacent...
A fully differential common-source cascode low noise amplifier(LNA) is presented for wireless receivers. The capacitive cross-coupling technique combined with cascode transistor is introduced to enhance LNA gain and reduce noise figure as well as the nonlinearity influence of cascaded transistors. A 2.6 mm long on-chip folded dipole antenna is integrated with this LNA and co-design is performed for...
The design highlight of a power amplifier (PA) for 3G and beyond handset applications is to maximize its power-added efficiency (PAE) with specified linearity requirement at both peak and back-off power levels. In addition to PAE, its cost and size are of very important design considerations among others. The design principle of a linear PA with good PAE is summarized. An overview of different GaAs...
The advanced modulation formats used in 3G and 4G mobile systems have pushed the need for improved power amplifier linearity. The multi-function capability and sleeker form factor design of today's smart phones have added more stringent requirements to the size and current consumption of power amplifier modules. This paper discusses some of the linear power amplifier module market trends and the technical...
A new method for extraction of series resistance is proposed for poly-Si thin-film transistors. In this method, the extraction procedure is insensitive to the variation in effective channel length and device mobility, since both quantities are included in a single extracted parameter. The method has been successfully applied to a group of poly-Si TFTs with mask channel length from 2 to 30μm. Compared...
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