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This paper presents an energy-efficient SoC dedicated for portable medical monitoring and intervention systems capable of closed-loop control. The SoC contains a 0.9V/165μW MCU and a dual-band RF block including a 403MHz transceiver for data link and a 915MHz receiver for wake-up link. The data link transceiver is composed of a 200kbps FSK transmitter and a 64kbps OOK receiver, consuming 5.58mW and...
This paper presents a technique to efficiently supply power over a wide power range using a fully integrated on-chip converter for dynamic voltage scaling (DVS) based applications. All components, including filter elements, are integrated onchip. To achieve high efficiency the converter adaptively switches between different modes of operation by detecting the output current. The design, implemented...
A 16×12-channel neurochemical microarray is presented. Each channel acquires bidirectional currents down to pico-amperes proportional to the concentration of a neurochemical. By combining the current-to-frequency and the single-slope analog-to-digital converter (ADC) 110dB of dynamic range is achieved. The ADC in each channel generates a 16-bit output in less than a millisecond. The microarray with...
Varactors can be used to control delays and limit ISI-related signal integrity degradation for on-chip global interconnect. This paper presents a varactor-based “near-speed-of-light” interconnect design. In this design, the varactors compensate for delay variations enabling a simple, source-synchronous solution for clock-and-data recovery. Furthermore, the varactors provide pulse shaping that reduces...
To address the “memory wall” challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins. To demonstrate the feasibility of 3D memory stacking, this paper...
A novel wideband 1-π equivalent circuit model for on-chip spiral inductors is presented. A substrate network, consisting of R/L/C, is proposed to model the broadband loss mechanisms in the silicon substrate. The skin and distributed effects for windings have been taken into account. A series of inductors with different geometries are fabricated in standard 0.18-μm 1P6M RF CMOS process to verify the...
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