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This paper presents a novel dual ladder resistor D/A converter architecture. A 10 bits D/A converter is implemented which is based on this architecture. The present architecture provides a novel decoding scheme for dual ladder resistor D/A converter that reduces the size of the decoding logic, reduces the number of switches in coarse resistor stage and fine resistor stage. Experience of the 10 bits...
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2...
A fourth-order continuous-time (CT) Delta-Sigma modulator with 1.5-bit quantizer is presented in this paper. This design is targeted for audio applications that demand high resolution, low supply voltage, and low power consumption. The input-feedforward topology, with optimized coefficients, is utilized to reduce internal signal swings as well as the power consumption. A 1.5-bit quantizer with simple...
Time-interleaved (TI) Analog-to-Digital Converters (ADC) are efficient for high-speed data acquisition. However, mismatches among different channels in a TIADC system due to manufacturing process variations cause distortion in the sampled signal and degrade the SNR and SFDR significantly. The offset and gain mismatches are the two important error sources for the TIADC system. In this paper, a methodology...
In this paper, the idea of variable resolution ADCs is proposed and implemented for all types of ADC architectures. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused sections of the ADCs to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADCs are capable of operating at 4-12 bit precision at a supply voltage...
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic...
It is very important that motion estimation can affect the quality of the video. Because it is easier to be realized in hardware, block matching algorithm (BMA) and compensation techniques have been widely used in video processing. But it is also the most computationally intensive module, which has limited the application. This paper proposes a novel octagon cross diamond search (NOCDS) algorithm,...
Motion estimation(ME) is one of the most important modules in digital video encoding/decoding and video post processing. High-quality and fast ME algorithms are desired by many applications. In this paper, motion estimation algorithms are explored in terms of execution efficiency on the CUDA (Compute Unified Device Architecture) technology which is a parallel computing architecture developed by nVIDIA...
In this paper, we propose a low-complexity motion estimation algorithm for frame rate conversion. Insteading of using sum of absolute difference (SAD) calculation, the algorithm adaptively uses simple comparison operation in different hierarchical motion estimation level to achieve good image quality and fast processing capability. Experiments are carried out on applying this algorithm for frame rate...
With the prevalence of video surveillance systems, the demand for video quality assessment in terms of blur is raised quickly. In this paper, a fast and effective method based on distribution of gradient magnitudes is proposed. The moving foreground regions are first extracted based on adaptive background mixture models. Detections of two types of blur, the global blur and the partial blur, are classified...
There are few methods to deal with the coal-mine surveillance video, the only few existing methods all make use of the traditional image engineering ideas. Visual attention has the prominent functions that can reduce computation and accelerate the computing speed. This paper firstly analyzes the limitations of existing down-top attention model in the application of coal-mine surveillance video, then...
Small target detection is widely used in many fields, such as environmental monitoring and assessment, space remote sensing, recognition and tracking of infrared target. In this paper, aiming at the problem of over-fitting and poor generalization capability in using artificial neutral network for small target detection, a new method is presented. First, it uses the structure element to set up training...
This paper presents a new digital background calibration algorithm for pipelined analog-to-digital converters (ADCs). Background calibration can extract calibration data without interrupting ADCs normal conversion operation. Digital calibration can relax the design difficulty of analog circuits of ADCs, and gains the improvement of technology scaled down. This algorithm provides a method to effectively...
A digital foreground self-calibration method, bases on the existing off-line calibration algorithm is presented. This work extends it to correct nonlinear effects of the op amps. It eliminates both linear and nonlinear errors, such as capacitors mismatch, comparator offset, finite op amp gain error, and op amp nonlinearity. The simulation shows that this work gives great improvements of 38.25dB and...
This paper presents a scheme of 14-bit 100MS/s pipelined analog-to-digital converters (ADCs) with digital calibration. Signal-dependent pseudo-random dithering has been used in the proposed model to measure the errors caused by finite gain and capacitors mismatch in multiplying digital-to-analog converters and correct them in the digital domain. Comparing with fixed-magnitude PN dithering, a signal-dependent...
In order to reduce the design difficulties, the input sample-and-hold amplifier (SHA) is often removed in the nested background calibration of the CMOS pipelined analog-to-digital converters (ADC). The system uses a dual-channel LMS adaptive digital background calibration algorithm, and the reference ADC was calibrated in the foreground. Without the input SHA, the sampling-time error between the two...
A 12-bits 40 MS/s pipeline analog-to-digital converter (ADC) in SMIC035um mixed-signal process is presented in this paper. The ADC adopts methods below to improve its performance, a novel bootstrapped switch is used to sample and hold circuit in order to improve the resolution of ADC, a residue amplifier with gain-boost to eliminate gain error. This ADC achieves a SFDR of 65 dB, a SNDR of 56 dB, a...
This paper presents a novel input/output interface circuit for field programmable gate array (FPGA) devices, which has high voltage tolerant and PCI compliant capabilities. In the proposed circuit, dynamic gate and N-well bias technology is used to eliminate gate-oxide overstress and Pad to output supply (Vcco) leakage current when FPGA devices operate with high voltage input, and to ensure that over-voltage...
This paper presents a design of 8B/10B encoder and decoder with a new architecture. The proposed 8B/10B encoder and decoder are implemented based on pipeline and parallel processing. The decoder implements an error-undiffusing function. This 8B/10B encoder and decoder can be used in the high-speed interconnection between chips. After being synthesized using CMOS 90nm process, the proposed encoder...
RapidIO is an emerging high-performance and point-to-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain...
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