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The following topics are dealt with: power electronics; digital circuits; data converters; video and image processing; wired communication; digital signal processing; analogue circuit; pipelined ADCs; RFID; RF and antenna; MEMS and sensors; biomedical circuits and systems; CMOS power regulator; GPS signal; telephone remote control system; VLSI interconnects; continuous-time delta-sigma modulator;...
Neutral point potential balance control is very important to three-level neutral-point-clamped (NPC) rectifiers. In this paper, the balance control strategy is studied with three-level space vector pulse width modulation (SVPWM) algorithm based on reference voltage decomposition. An improved neutral-point potential balance control strategy based on balance factor is proposed and the principle is analyzed...
This paper introduces the working principle of space vector pulse width modulation (SVPWM), and presents a new circuit realization of SVPWM generator based on FPGA-embedded technique. MicroBlaze is a 32-bit high-performance processor embedding in the FPGA chip, and the left logical units can be used to design IP cores that needed, thus software and hardware can be combined to realize this SVPWM control...
This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5 v to 5.0 v with 0.1 v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation...
A novel wireless powering solution for active capsule endoscope has been presented in this paper. The self-resonant coil inside the human body is used to receive energy, and the energy is rectified and regulated to generate a stable voltage for charging a button battery, which provides stable power for controlling and driving the system by the low dropout (LDO) regulator fixed in the capsule endoscope...
In this paper, we present the design of a low-power, high-power supply rejection ratio (PSRR) power regulator used in telemetry-powered bioimplantable microsystems in a 0.35μm standard CMOS process. The power regulator is comprised of a CMOS full-wave bridge rectifier, a wide-range and high PSRR voltage reference and a low drop out series voltage regulator. Simulation results show the proposed circuit...
In this work, a method for estimation of the switching activity in integrators is presented. To achieve low power, it is always necessary to develop accurate and efficient methods to estimate the switching activity. The switching activities are then used to estimate the power consumption. In our work, the switching activity is first estimated for the general purpose integrators and then it is extended...
This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption...
A low power dual-supply dual-ground voltages domino circuit is presented in this paper. The domino circuit employs a high ground voltage and the shared-well technique to improve the dual-supply voltage technology and further reduce the power consumption and optimize the layout area. Based on Chartered 0.35 um 2P4M CMOS technology, simulation results shows that dual-supply dual-ground voltages domino...
A sense amplifier D flip-flop with reset function using energy recovery technique, SAERDR (Sense Amplifier Energy Recovery D Flip-flop with Reset Function), is presented. The proposed flip-flop operates with a single phase sinusoidal clock to recover the energy of the clock pin. Simulation results show that the power consumption of clock pin is saving 72% on average as compared to the same implementation...
This paper presents an intelligent control system with the ability of remote control based on a public telephone communication network. The remote operation with user authority by transmitting password and operation code through telephone network is realized by using a FPGA controller. The main function circuits of the designed system include ring detector, DTMF decoder, pick-phone circuit, audio...
This paper presents a swarm Intelligence based circuit partitioning technique using particle swarm optimization method. The circuit is divided into partitions and number of interconnections between them is minimized. The proposed method gives excellent results in solving the stochastic problem of circuit partitioning.
Embedded applications usually impose tight constraints upon their code efficiency, which entail elaborate code optimization on the hotspot of the programs. In order to identify the hotspot, we propose an effective and easy-use loop-centric profiling method in this paper. In our proposed method, a code isolation step is first applied on the original code, which extracts all the candidate loops at source...
This paper proposes an efficient VLSI extraction algorithm to extract a transistor level netlist to a gate level netlist for functional verification and diagnosis. Compared with other reported circuit extraction algorithm, our proposed technique does not require a cell library and is able to generate Boolean equations without the prior knowledge of transistor type or drain/source orientation of the...
Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. The flexibility of ASIPs makes them preferable over fixed function Application Specific Integrated Circuits (ASICs). Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASlP design is a limiting...
Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. However designing an ASIP is complicated by the fact that not only the processor but, also tools such as assemblers, simulators, and compilers have to be designed. Novel Generator of Accelerators And Processors (NoGap), is a design automation...
This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper also shows that the...
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