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The following topics are dealt with: power electronics; digital circuits; data converters; video and image processing; wired communication; digital signal processing; analogue circuit; pipelined ADCs; RFID; RF and antenna; MEMS and sensors; biomedical circuits and systems; CMOS power regulator; GPS signal; telephone remote control system; VLSI interconnects; continuous-time delta-sigma modulator;...
This paper introduces the working principle of space vector pulse width modulation (SVPWM), and presents a new circuit realization of SVPWM generator based on FPGA-embedded technique. MicroBlaze is a 32-bit high-performance processor embedding in the FPGA chip, and the left logical units can be used to design IP cores that needed, thus software and hardware can be combined to realize this SVPWM control...
This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption...
This paper presents an intelligent control system with the ability of remote control based on a public telephone communication network. The remote operation with user authority by transmitting password and operation code through telephone network is realized by using a FPGA controller. The main function circuits of the designed system include ring detector, DTMF decoder, pick-phone circuit, audio...
Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. The flexibility of ASIPs makes them preferable over fixed function Application Specific Integrated Circuits (ASICs). Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASlP design is a limiting...
This paper presents a novel input/output interface circuit for field programmable gate array (FPGA) devices, which has high voltage tolerant and PCI compliant capabilities. In the proposed circuit, dynamic gate and N-well bias technology is used to eliminate gate-oxide overstress and Pad to output supply (Vcco) leakage current when FPGA devices operate with high voltage input, and to ensure that over-voltage...
An optimized architecture is proposed for real-time automatic cloud detection system with Spectrum and Texture Analysis Combination (STAC) approach. The STAC approach is hard to be implemented in hardware, for the calculation of fractal dimension (FD) and angle second moments (ASM) of the approach consumes large computation time and hardware resources. By optimizing the calculation process of the...
In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms...
Advanced Encryption Standard (AES) is one of the latest symmetric key cryptosystem standard, which is proposed to replace DES. Whirlpool is a famous hash encryption algorithm that processes the building blocks in a similar way. Although some slight differences are presented, implementing an integrated design of AES and Whirlpool on the FPGA can reduce the overall area. Further more, it provides a...
A proposed UHF RFID location system, based on a known location of the reference tags by applying the cosine theorem to calculus more location information, can provide location-aware services. In this article, the trigonometric cosine and sine functions required in the computation of the law of the cosines are realized using a Coordinate Rotation Digital Computer (CORDIC) based floating-point arithmetic...
In this paper, we study the RFID tag-reader mutual authentication scheme. A hardware design of an RFID authentication protocol conforming to EPC Class 1 Generation 2 Standards is proposed. The proposed RFID tag-reader mutual authentication protocol was simulated using Modelsim XE II and synthesized using Altera's Quartus II software. The system has been successfully verified in hardware using an Altera...
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