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Various high speed sequential multi-threshold voltage CMOS (MTCMOS) circuit techniques are presented and evaluated in this paper. Dedicated low leakage data preserving memory elements are integrated into the MTCMOS flip-flops. The leakage power consumption of an MTCMOS memory register is reduced by up to 67.72% as compared to the previously published conventional sequential MTCMOS circuits in a UMC...
Ground bouncing noise produced during reactivation events is an exacerbating challenge to maintain accurate logic levels in Multi-threshold CMOS (MTCMOS) circuits. A new noise-aware MTCMOS circuit with dynamic forward body bias is explored in this paper to minimize the ground bouncing noise with smaller sleep transistors. The dynamic-forward-body-biased MTCMOS circuit lowers the peak ground bouncing...
A new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC) is presented. The new offset averaging design technique takes full advantages of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance...
In this paper, we demonstrate that by introducing a high tensile Inter Layer Dielectric (ILD) in the fabrication process, the hook shaped saturation drain current (Idsat) behavior of NMOS can be reduced and totally eliminated in PMOS for 0.13um technology node. The hook shaped Idsat behavior is caused by the combination of mechanical stress due to Shallow Trench Isolation (STI) in channel width direction...
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