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We present a methodology, based on genetic algorithms, that optimizes shared heterogeneous Memory BIST architectures with regards to area, testing peak power and test time.
Testing of mixed-signal SoCs becomes one of the pressing challenges due to enormous test cost including ATE expenses, design for test (DFT) hardware overhead and test application time. Prior researches focus mainly on minimizing test cost for digital SoCs under the constraint of ATE test resources and power consumption. A self-hold analog test wrapper design and pipelined parallel test manner are...
In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible...
In this paper configurable fault tolerant links are proposed for inter-die communication in stacked 3D SoCs. For high TSV fault rates, links degrade their performance by serial data transmission and signal remapping on the defect free wires. The link degradation is limited to a predetermined value, above which the link is considered non-functional.
Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells...
Timing-aware ATPGs are being developed to detect small delay faults for high defect coverage for current nanometer VLSI design. However, it results in a large test set compared with test generation targeting traditional fault models. This paper proposes a method to get a limited size of test set with high delay test quality based on statistical delay quality level (SDQL).
This work explores the concept of design diversity redundancy applied to mixed-signal (MS) circuits. Results from fault injection experiments show a very good ability of the system to tolerate double faults.
We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is...
Health and usage monitoring (HUMS) as a technique for online test, diagnosis or prognosis of structures and systems has evolved as a key technology for future critical systems. The application of HUMS technology requires a portfolio of reliable miniaturized sensors, capable of delivering "intelligence" on the internal and external environment of a system or structure. This paper proposes...
The paper presents a novel programmable Built In Current Sensor (BICS) topology in IBM 65 nm CMOS technology. Proposed topology has 2.086 GHz bandwidth and 38.9ps detection time. Moreover, a new built-in IDDQ test flow is proposed. Proposed test flow is applied to a charge pump. The results show 100% fault coverage for the defects that affects the output of the charge pump (CP). 97.87% overall fault...
Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction...
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