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Summary form only given. One of the driving forces behind the semiconductor industry has been Moore's law. In abstract Moore's law says the number of transistors per square inch on integrated circuits will double every 18 months. Doubling transistor count in rough approximation doubles complexity. To keep the same cost, yield at the new process node must be similar to the previous node. Further, to...
The functions required of real-time systems in the future such as the ability to see or hear, understand and react to external stimulus and the environment in much the same way that humans do, will force underlying communication and computing platforms to operate across very large changes in instantaneous workload. Supporting such workload variations on resource-constrained mobile systems will require...
This paper describes the development of adaptive test in response to the ever growing need to dynamically and cost effectively tailor IC testing to discriminately manage manufacturing process variations. Various degrees of adoption are presented, together with benefits and examples of it's use. Finally, challenges for future development are discussed.
Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded...
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology. We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are NP-hard...
Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan...
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers...
In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then...
The paper discusses a variety of sensors to enable a built-in test in RF devices. The list of sensors includes dummy circuits, process control monitors, DC probes, an envelope detector, and a current sensor. Dummy circuits and process control monitors are simple circuits that do not tap into the signal path of the RF device. Instead, they monitor the device by virtue of being subject to the same process...
This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated,...
Scan is a known design-for-test technique in manufacturing test that has been successfully applied also to aid post-silicon debugging on testers. However, to achieve real-time observability in-field, embedded trace buffers are needed. In this paper, we discuss how in the presence of enhanced scan chains, trace buffers can be utilized efficiently for real-time debug data acquisition in-field.
Increased die-to-die and on-die variations in scaled technologies can lead to parametric failures (Read/Write/Access) in embedded SRAMs. Conventionally, SRAM bit-cell failure analysis is based on the Static Noise Margin (SNM), a metric that leads to conservative estimate of design yield. In this paper we present a method of dynamic noise margin (DNM) estimation based on the modeling technique developed...
Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections...
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