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As the number of cores in a chip increases, the role played by the communication system becomes more and more central. An on-chip communication infrastructure based on the Network-on-Chip (NoC) paradigm is today recognized as the most effective and scalable solution able to deal with the communication issues that will characterize the next generation of many-cores architectures. An ever more significant...
Time-Division-Multiplexing (TDM) Virtual Circuit (VC) has been proposed to guarantee the Quality-of-Service requirements in communication for Network-on-Chip. In this paper, we explore the design space of slot allocation for configuring TDM VCs. Specifically, we investigate different slot assignment schemes, namely, distributed, random and consecutive schemes, which have significant impact on the...
Mapping of applications onto multiprocessor system-on-chip (MPSoC) can be realized either at design-time or run-time. At any time the number of tasks executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping techniques to meet the real-time constraints of the applications. This paper presents two run-time mapping heuristics for mapping the tasks of an application...
A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scalability and feasibility superior to existing similar techniques. With high-level simulation using 65...
Different power management techniques have been developed to target leakage-reduction at runtime of a design by orders of magnitude. To advance an optimization, different power modes and especially costs of state transitions have to be considered in early steps, e.g. during scheduling, allocation and binding of high-level synthesis. We present an operation scheduling, binding and allocation approach...
In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance of critical paths delay and efficiently meet timing constraints and thus improve timing yield. Experiments...
High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology...
In this paper we present constant multiplication architectures for the residue number system (RNS) moduli set {2n-1, 2n, 2n+1} using the signed-digit (SD) representation for recoding the constant operand. The resulting circuits require a small number of partial products, hence, their area and delay is also small.
3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates temperature-induced problems that affect system reliability, performance, leakage power and cooling cost. In addition, the overhead due to through-silicon-vias (TSVs) and scribe lines contribute to the overall area, affecting wafer...
An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150 MS/S sampling rate and dissipating 34 mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration method of such an ADC in order to extend its operational temperature range and correct the effect of mismatch and process variations...
This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65 nm CMOS IV technology, under the large capacitive loading condition (16pF), xb-ad performs...
Several parallel applications in MPSoCs take advantage of multicast communication. Path-based multicast scheme has been proven to be more efficient than the others multicast schemes in on-chip interconnection network. We present a new adaptive path based model for both the multicast and unicast wormhole routing protocols. The proposed model under mixed traffic models has lower latency than the previous...
This paper addresses the design issue of System-on-Chip by elevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedicated to the Modeling and Analysis of Real-Time Embedded systems. From user-defined models, information are extracted, which serve for the analysis of the models. The adopted analysis technique relies on the synchronous...
In this paper, we propose an architecture, which we call GridRT, capable of dealing with the main features, such as shadows and reflections effects, of Ray Tracing used for rendering three-dimensional scenes. This architecture achieves an efficient overall performance yet using a simple and compact massively parallel design. The design exploits the usage of Xilinx?? Floating Point Operator IP Core...
This paper presents an innovative way to build flexible benchmarks based on micro-architecture independent characteristics. The proposed approach enables the testing and stressing of processors in order to reflect the real nature of applications and give meaningful information to the designers. The use of a limited number of basic blocks hand-coded in assembly, wisely chosen and arranged, enables...
The design space of integrated circuits grows due to the need of fault recognition and error compensation. To meet reliability requirements, several reliability increasing methods have to be evaluated. We present a reliability estimation process which allows estimating the resulting reliability of a modified circuit without the need of synthesis. For further speed up, synthesis results after choosing...
Dependability is becoming a key design aspect of today networked embedded systems (NES's) due to their increasing application to safety-critical tasks. Dependability evaluation must be based on modelling and simulation of faulty application behaviors, which must be related to faulty NES behaviors under actual defects. However, NES's behave differently from traditional embedded systems when testing...
The concept of fault model free diagnosis is combined with cause-effect analysis in digital systems represented as networks of functional blocks. We consider the diagnosis as a task to locate a faulty block in the network by using concise block level topological fault dictionaries. The dictionary does not need fault simulation and represents only the connectivity of blocks to observable checkpoints...
Multicore and many core processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementation of 2 applications into an Ambric massively parallel processor array from a hardware design point of view. An evaluation of performance and design effort is provided, showing that massive parallel processor arrays may...
Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating during tests, we propose a thermal-aware test scheduling technique for core-based SoC in an abort-on-first-fail (AOFF) test environment. The AOFF environment assumes that the test process is terminated as soon as the first fault...
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