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Currently, the guaranteed throughput of a stream processing application, mapped on a multi-processor system, can be computed with a conservative dataflow model, if only time division multiplex (TDM) schedulers are applied. A TDM scheduler is a budget scheduler. Budget schedulers can be characterized by two parameters: budget and replenishment interval. This paper introduces a priority-based budget...
3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates temperature-induced problems that affect system reliability, performance, leakage power and cooling cost. In addition, the overhead due to through-silicon-vias (TSVs) and scribe lines contribute to the overall area, affecting wafer...
This paper addresses the design issue of System-on-Chip by elevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedicated to the Modeling and Analysis of Real-Time Embedded systems. From user-defined models, information are extracted, which serve for the analysis of the models. The adopted analysis technique relies on the synchronous...
The design space of integrated circuits grows due to the need of fault recognition and error compensation. To meet reliability requirements, several reliability increasing methods have to be evaluated. We present a reliability estimation process which allows estimating the resulting reliability of a modified circuit without the need of synthesis. For further speed up, synthesis results after choosing...
Dependability is becoming a key design aspect of today networked embedded systems (NES's) due to their increasing application to safety-critical tasks. Dependability evaluation must be based on modelling and simulation of faulty application behaviors, which must be related to faulty NES behaviors under actual defects. However, NES's behave differently from traditional embedded systems when testing...
Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization...
Fault simulation of the asynchronous sequential circuits is more complicated than fault simulation of their synchronous counterparts. It needs to deal with hazards, oscillations and races. The complex gates in the asynchronous circuits are another challenge especially for deductive fault simulation. In this paper a deductive fault simulator for the speed-independent (SI) asynchronous sequential circuits...
In this paper the design and simulation of a single-electron 2-4 decoder based on NAND gates is presented. The simulation was made using a Monte-Carlo based tool. The results confirmed that the circuit was behaving as a 2-4 decoder. The stability plot and the free energy history diagrams offer detailed analysis of the circuit. The results were compared to similar circuits reported in the literature...
Constant evolution of norms and applications, usually implemented on system-on-chip (SOC), increases architecture performance and flexibility requirements. Current architectures are consequently becoming more complex and difficult to develop. One of the solutions is to develop design frameworks based on high-level architecture description languages (ADL). These ADLs are useful for a rapid description...
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