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Summary form only given. High-performance chip-to-chip signaling is a challenging requirement of many modern VLSI systems and with ITRS predictions of 160-Gb/s serial I/O and 40-Gb/s parallel I/O links by 2016 it is likely to remain so. There has recently been a proliferation of signaling standards such as PCI Express, XAUI, RapidIO, Interlaken, and others making it difficult for practicing engineers...
The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved multiplier performance. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a limited impact on overall performance. The Baugh-Wooley algorithm...
Gain and timing mismatches among sub-converters limit the performance of time-interleaved analog-to-digital converters (TIADCs). In this paper we present a blind adaptive method, based on the least-mean-square (LMS) algorithm, to compensate gain and timing mismatches in TIADCs. Similar to other methods in the literature, we assume a slightly oversampled input signal, but, contrary to them, we can...
4-bit 2-Gsample/s flash A/D converter is presented. It is realized in a digital 0.13 um CMOS technology. To compensate for timing skew and delay problem at comparator outputs, a new latched-skewed-logic is introduced; the proposed latched-skewed-logic improves the performance of the A/D converter with negligible increase in power consumption. The simulation results show that the implemented A/D converter,...
This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast...
Caches in embedded systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches. This is a critical problem in real-time systems, where tight worst case execution time (WCET) is required for their schedulability analysis. Several works have studied the data cache impacts on the WCET...
C-based hardware-accelerated embedded system has been proposed to tackle the increasing time-to-market pressure and the growing complexity of system on chip (SoC). Due to tools selection and different set of synthesis, place and route options, numerous low level solutions in term of area and frequency can be produced and must be considered in high abstraction level. In this paper we conduct a quantitative...
Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part...
CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where...
This paper investigates the signal integrity and performance of a novel programmable interconnect technology called DreamWafertrade. This programmable circuit board uses a wafer-scale circuit with a sea of tiny contacts to adapt to the contact type, size, spacing and alignment of external components. Supporting this ability to adapt requires a dense internal programmable interconnect network to propagate...
A delay-insensitivity analysis method is proposed for bit-level pipelined systolic arrays in dual-rail threshold logic style, where tradeoff between reliable delay insensitive operation and gate count is significant in determining overall circuit performance. The method targets at detecting input - dependent delay-insensitivity violations occurring due to early signal evaluation features, which are...
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