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The area, delay and power consumption of functional units all are dependent on the word-length of the processed data. Since choosing an optimum word-length is a tradeoff between design costs and accuracy, it is essential to have an accurate model of computational errors for each operation. Errors resulting from the output rounding or truncation of the functional units is generally considered as uniformly...
Entropy coding is a fundamental stage in all video compression algorithms in terms of compression efficiency and error resilience. In this paper we propose and optimize a digital signal processor (DSP)-based implementation of the CAVLC tools for the H.264 Baseline encoder. As result, we have been able to generate the bit stream and supply bit rate result: the LETI encoder is able to achieve high compression...
Energy scavenging systems (ESS) can be important, theoretically endless, sources of energy. In the future, they could recharge or even replace batteries. In this paper a design methodology is presented in order to maximize the harvested energy and the transduction efficiency of a cantilever-like piezoelectric scavenger. The role of geometrical parameters is investigated through a theoretical analysis...
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially...
The performance simulation of embedded system designs is often a time consuming process. Whereas the simulation performance of hardware models depends on the chosen abstraction level, the software part is usually simulated with a slow instruction-set-simulator (ISS), which greatly limits the entire simulation speed. In this paper we solve this problem by presenting a highly automated methodology developed...
This paper describes a design of a switched capacitor common mode feedback (SC CMFB) folded cascode operational transconductance amplifier for low power and high-speed sigma-delta modulators. An algorithmic driven methodology is developed ending to the optimal transistor geometries. Using a 0.35 mum CMOS process, the OTA circuit has been designed to achieve 82.94 dB DC gain, 526 MHz unity-gain frequency,...
For a given floorplan in hierarchical power quad-grids(HPQGs) with the IR-drop constraint and the electromigration constraint, an iterative two-phase approach is proposed to design reliability-driven HPQGs to assign limited power pads and power wires to supply the required current and satisfy the current density constraint for each power branch and the IR-drop constraint for each power node with minimizing...
Layout design of analog and mixed-signal circuits is often a manual and time-consuming, trial-and-error task. Stringent constraints that must be considered simultaneously are a major reason why layout design is often not automated. To overcome this bottleneck in the design process, we present a new constraint-driven design methodology. We have verified our methodology by applying it to the placement...
This paper concentrates on designing two-channel filterbanks (FBs) with rational sampling factors based on using infinite-impulse response (IIR) filters. In order to generate FBs having a low implementation complexity, a special structure for the IIR filters is utilized, which enables one to evaluate the recursive part of the IIR filters at the subband sampling rate, that is, at the lowest sampling...
The research developed in this paper lies in the framework of the Wireless Power Transportation (WPT) applied to the RFID. The carried study aims at to obtain the best efficiency of the collecting/rectifying part of the WPT system (rectenna) where recovery of the microwave energy into continuous energy takes place. The optimization is performed on an equivalent circuit approach of the rectenna with...
A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational...
This paper introduces a new methodology for optimizing the performance of asynchronous-linear pipelines. The method supports all delay types, static and variable time delays, enabling the designers to optimize their architecture taking into account the timing information of data dependencies, circuit structure and process variations. The method not only determines the minimum degree of pipelining...
Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability to considerably improve both the fault coverage and...
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