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A new approach for diagnostic analysis of bandwidth mismatch in time-interleaved systems based on gradient search method is proposed. The algorithm is adaptive to slow changes in mismatch errors and does not require any information about the input signal. Additionally, the information acquired can be re-used to supplement the circuit calibration. The proposed method is evaluated on a prototype sample-and-hold...
A low-voltage low-power bandgap voltage reference without using passive components is presented. Using piecewise linear curvature-compensated scheme, a reference voltage of 646.4 mV is generated with a temperature coefficient of 1.7 ppm/degC in the range [-40, +125] degC at 1.8-V supply voltage. A line sensitivity of 0.18 mV/V in the supply voltage range [+1, +1.8] V is achieved. It dissipates a maximum...
High performance and computational capability in the current generation processors are made possible by small feature sizes and high device density. To maintain the current drive strength and control the power dissipation in these processors, simultaneous scaling down of supply and threshold voltages is performed. High device density and low threshold voltages result in an increase in the leakage...
This paper describes the design of voltage controlled oscillator (VCO) with a low-power static frequency divider. The new LC-VCO replaces one of the NMOS of a conventional differential LC-VCO with a PMOS, which reduces power dissipation to the half and allows operation at reduced supply voltages. Based on a 0.13um UMC CMOS process, the VCO is simulated using 0.8V supply voltage. It is demonstrated...
A low-voltage low-power pacemaker Front-End for detecting QRS complex is presented in this paper. The circuit includes a switched-opamp switched-capacitor (SO-SC) preamplifier with a gain of 40 db, a fourth-order Butterworth SO-SC filter with a sampling frequency of 1 kHz, and an opamp with a new continuous time common mode feedback (CMFB) circuit which is able to operate with a very low supply voltage...
This paper presents a model of the frequency sensitivity to the control voltage (Kvco) of a ring oscillator. The proposed model is devoted to the PMOS symmetric load Ring oscillator. An example considering a 2.5 V CMOS 65 nm is presented where the accuracy of the results are presented and compared to those obtained using ELDO simulator.
A new adaptation scheme for low noise and fast settling 50 MHz analog phase-locked loop (PLL) is presented. According to the locking status, an extended loop bandwidth enhancement is achieved by the adaptive contol on the charge pump current. First of all, when the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand,...
In this paper the design and measurement of a high-speed optical receiver, completely integrated in a standard 130 nm CMOS technology, is described. The low optical bandwidth of the integrated photodiode has been alleviated with a differential photodiode topology and an optimized equalizer. The photodiode has a large parasitic capacitance of 1 pF at each of its outputs and a responsivity of 3.4 mA/W...
Monolithic switching buck (step-down) converter is designed on standard 0.35-mum CMOS process. Different control techniques such as Pulse-Width Modulations (PWM) and Pulse-Frequency Modulations (PFM) are investigated. The received results show that PFM control indicates higher efficiency at light-loads compare to standard constant frequency PWM control. Efficiency of about 76% is achieved for the...
This paper proposed a novel controlling technique of pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode to keep the high efficiency within width range of loading. The novel control method is using PWM and PFM detector to achieve two modes switching appropriately. The controlling technique can make the efficiency of current mode DC-DC buck converter up to 88% at light loading...
In this paper, we present a novel high speed binary phase detector for clock and data recovery (CDR) applications. We also introduce a new probable-lock detector which is used to alleviate the classic tradeoff between acquisition time and jitter. The probable-lock detector is used in the CDR to generate a higher gain during the acquisition process and reduce this gain when clock and data are locked...
This paper presents a CMOS reconfigurable translinear cell intended to be part of a field programmable analog array. The cell is composed of a recently developed wide dynamic range translinear element and programmable current sources, current mirrors and capacitors. An FPAA built with this cell is able to implement the most common primitives of translinear design, such as, multiplication, division...
A proposed configurable analog block (CAB) is presented, simulated and analyzed. The CAB consists of a CMOS current feedback operational amplifier (CFOA), presented by the authors, as the main active block, programmable resistor array, programmable capacitor array and MOSFET switches. Using the CABs, the universal field programmable analog array (FPAA) has been constructed, which can realize many...
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