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Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for...
This paper presents a design solution that enables the use of powerful multi-bit error-correcting code (ECC) to realize L2 cache defect tolerance at minimal latency and silicon area cost. This work is motivated by the observation that the continuous CMOS Technology scaling may result in an increasing level defect density and make conventional cache memory defect tolerance strategies inadequate. The...
We present an adaptive error control method for switch-to-switch links in a variable noise environment, to meet reliability requirements and achieve energy-efficiency. Unlike worst-case error correction coding (ECC), the proposed method is capable of selecting the most effective ECC scheme based on predicted link quality at runtime. Our method configures the ECC codec to obtain the desired error correction...
With the complexity of the integrated circuit designs increasing along with the shrinking of the technologies with each passing generation, the vulnerability of these components increases.The sensitivity to transient faults caused by noise, extra terrestrial rays etc. are a cause of concern and require mitigating circuits in any cutting edge of technology. These problems can affect the storage as...
In this paper we propose a mitigation technique for the protection of critical data in electronic devices from Single Error Upsets (SEU) that manifest themselves as bit-flips in memory. In order to cope with this problem, we take advantage of convolutional codes. We propose a methodology to generate a light decoder architecture considering all the possible combinations of generator polynomials of...
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