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Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we...
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