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Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
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