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The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and power constraints. However due to continued scaling of process technologies, the devices and interconnects have become more susceptible to single event upsets. This paper presents a low cost error correcting code based technique...
This paper presents a new routing protocol of network-on-chip(Noc) called "Source Routing for Noc" (SRN) for fault tolerant communication of Systems-on-chip(Soc). The proposed SRN algorithm is composed of two mechanisms of route discovery and route maintenance to allow nodes to discover and maintain source routes to arbitrary destinations in Noc, and all aspects of the protocol operate entirely...
This paper presents an efficient method for online testing of NoC switches. This method deals with control faults of NoC switches; i.e. the routing faults which cause NoC packets to be sent to output ports not intended to. A high level fault model has been proposed in this paper to model switch routing faults. The proposed method is evaluated by fault simulation that is based on our high-level fault...
In this paper, we present the design of a new architecture tolerating faults for the Image compression standard JPEG2000. The proposed fault tolerant design is based on adding a new reconfigurable core to the rest of the cores of the SoC. When a fault happens, it is tolerated using this reconfigurable core. The paper explains the hardware architecture allowing this inter-core communication toward...
Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system and cost-effective reliability improvements. In this paper we present an approach to obtain uncertainty bounds on the error propagation probability (EPP) values used in SER estimation based on an analytical approach. We demonstrate how we can compute EPP values and their uncertainty...
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output of a gate, which in turn can propagate to a register and cause a single event upset (SEU) there. Circuit level modeling and analysis of SETs provides an attractive compromise between computationally expensive simulations...
During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing "open" and "short" defects to interconnects. In this paper, a third type of defects called "interconnect narrowing" defect is defined. Interconnect narrowing occurs when a defect intervenes the lithographic printing of interconnects causing the formation of a narrow interconnect...
Single event transient (SET) fault analysis is usually performed trough digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an approach to build an FPGA based SET emulator, which implements a quantized delay model of the circuit under evaluation. Experimental results demonstrate...
We present an experimental analysis of the sensitivity of SRAM-based FPGAs to alpha particles. We study how the different resources inside the FPGA (LUTs, MUXs, PIPs, etc. ) are affected by alpha-induced SEUs, assessing the cross section for the configuration memory cells controlling each of them. We then show two case studies, a chain of FIR filters and a series of soft microcontrollers implemented...
This paper presents the adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique...
In this paper the design of a FIR filter with self checking capabilities based on the residue checking is analyzed. Usually the set of residues used to check the consistency of the results of the FIR filter are based of theoretic considerations about the dynamic range available with a chosen set of residues, the arithmetic characteristics of the errors caused by a fault and on the characteristic of...
SRAM based reprogrammable FPGAs are sensitive to radiation-induced single event upsets (SEU), not only in their user flip-flops and memory, but also in the configuration memory. Appropriate mitigation has to be applied if they are used in space, for example the XTMR scheme implemented by the Xilinx TMRTool and configuration scrubbing. The FLIPPER fault injection platform, described in this paper,...
Fault injection is needed for different purposes such as analyzing the reaction of a system in a faulty environment or validating fault-detection and/or fault-correction techniques. In this paper we propose a simulation-based fault injection tool able to work at different abstraction levels and with user-defined fault models. By exploiting the facilities provided by a functional verification environment...
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