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We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high tensile-stressed UV film in conjunction with stress memorization techniques (SMT). For the first time we demonstrate that using a UV-cured tensile film allows a 6% performance boost on the SOI NMOS, achieving a drive current of ~1170 muA/mum (1250, non-self-heated)...
We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.
We have demonstrated NMOS FinFET devices with a Vt of 0.33V through As implantation into TiN. The method allows for multiple Vt FinFET devices with Vt's of 0.33V, 0.55V (NMOS) and -0.35V (PMOS) through just one As implantation step into lOnm TiN. The NMOS Vt can be further modulated by adjusting the As implantation dose. Further optimization of the cap, implantation and annealing conditions will be...
A novel Si-on-SiC hybrid substrate is demonstrated using MOSFET devices. This is the first demonstration ever of this technology, to the best knowledge of the authors. The direct bonded substrate uses polysilicon as an intermediate layer, thereby eluding the thermally unfavourable SiO2. The MOSFET characteristics as well as the absence of self-heating effects are shown and are benchmarked against...
In this work, we investigate the possibility of achieving low VT nMOS FinFETs with single metal gate by using a dysprosium oxide (Dy2O3) cap layer inserted between gate dielectric and metal. We determine an optimum ratio between Dy2O3 and SiO2 gate dielectric thicknesses for low nMOS VT with good process margin and no loss in performance and reliability.
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