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In this paper, we report for the first time electrical performances of high hole mobility pMOSFETs with high-k/metal gate using ultra-thin GeOI wafers as templates obtained by the Ge condensation technique. It is concluded that the results coupled with a localized Ge condensation technique, open the way to planar SOI-nMOSFET/GeOI-pMOSFET co-integration.
We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.
This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.
We have demonstrated NMOS FinFET devices with a Vt of 0.33V through As implantation into TiN. The method allows for multiple Vt FinFET devices with Vt's of 0.33V, 0.55V (NMOS) and -0.35V (PMOS) through just one As implantation step into lOnm TiN. The NMOS Vt can be further modulated by adjusting the As implantation dose. Further optimization of the cap, implantation and annealing conditions will be...
In this work, the usefulness of gate-underlap design to overcome the degradation of analog/rf FOMs (figures of merit) has been analyzed for ULV applications. For a device designed with d=5 nm/dec, the spacer widths in the range or 20- 50 nm represents lateral straggle values in the desired range of 10-15 nm independent of gate length to achieve significant improvement in analog FOMs. The optimal values...
In this paper we present for the first time essential building blocks for RF circuits in an advanced FinFET technology. Voltage controlled oscillators (VCOs) and a low noise amplifier (LNA) have been realized.
This paper presents the operation of uniaxially strained SOI nMOSFETs at cryogenics temperatures with emphasis in the most common analog figures of merit as the intrinsic gain, output conductance and linearity.
A framework for accurately determining the device currents in trapezoidal FinFET devices is presented. The analytical formulation also computes the equivalent threshold voltage of an ideal rectangular fin with iso-current characteristics. The approach easily lends itself to the sensitivity analysis of device currents to variations in the geometric parameters.
A methodology for evaluation and optimization of quantization error when porting a pre-existing planar design to FinFET technology is presented. A 52-bit adder from a general purpose processor is used to illustrate the key findings of this study.
In PD-SOI the oxide layer between MOSFETs and the underlying silicon substrate presents a thermal resistance that can lead to significant temperature rise for power dissipating devices. This can impact circuit performance and also introduce differences between device characteristics measured under DC conditions and those experienced under "at speed" operating conditions with low duty cycles...
This work reports on the modeling of the unique subthreshold characteristics of the AM-MOSFETs and the implementation to the device to control the subthreshold characteristics and electrical stress immunity. Subthreshold characteristics degradation due to hot carrier stress can be significantly suppressed by tuning the device to the bulk current controlled device. Moreover, scalability of the accumulation-mode...
The geometric magnetoresistance (MR) is reproduced by Monte Carlo simulations and used to accurately extract the carrier mobility. This original method allows comparing the transport mechanisms in various cases of interest: single-gate (SG) versus double-gate (DG) operation, Si-high-K versus Si-SiO2 interfaces, in-depth inhomogeneous transport. When both front and back channels are activated, our...
This paper demonstrates some interesting attributes of an ultrathin DT-MOSFET that has a confined structure; the bipolar action is suppressed or enhanced by the gate following the mechanism of Lubistor operation. It is concluded that a DT-MOSFET suitable for low-power and low-noise circuit applications can be realised.
This paper describes the temperature behavior of the phonon-limited electron mobility on the (111) and (001) Si surfaces of DG SOI MOSFET. We discuss the major difference of the phonon-limited electron mobility behavior on the (111) and (001) Si surfaces of DG SOI MOSFET at low temperature.
Flexfet is a new SOI IDG-CMOS technology with a damascene metal top gate and an implanted JFET bottom gate that are self-aligned in a gate trench. The independent top and bottom gates are contacted at opposite sides of the channel by a local interconnect that is embedded in the isolation region between devices. A simple analytical dynamic threshold voltage model is developed and verified by extensive...
Strained silicon-on-insulator (sSOI) was exposed to high-temperature (1200-1350degC) annealing and high-dose 60Co gamma-ray irradiation (51.5 kGy) to study the tenacity of the bond between the strained Si film and the underlying buried oxide. All samples were characterized by UV Raman, pseudo-MOSFET (psi-MOSFET) current-voltage, Hall mobility, and photoluminescence (PL) to verify any change in strain...
Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for the I/O and HS SOI p-channel MOSFETs. I/O PMOS devices...
Integration of fully-depleted SOI (FD/SOI) MOSFETs for high performance 3.3 V/2.5 V I/O applications in contemporary high-performance partially-depleted SOI (PD/SOI) CMOS is reported for the first time. The FD/SOI MOSFETs feature dual etch-stop layer (dESL) stressor, optimized (minority) carrier lifetime killing implant in source/drain extension, and optimized in-situ steam generated (ISSG) gate oxidation...
Thermal effects on different tiers of wafer-scale three dimensional (3D) integrated circuits were examined. The temperature was measured using pn diodes, and the heating effects on the characteristics of MOSFETs were compared. It is found that the circuit at the top of the 3D stack is the hottest. Adding metal plugs through the buried oxide or placing metal heat sink at the top surface improves heat...
Based on 3D numerical simulations and on a technological evaluation, we demonstrate the relevance of a new stacked nanowires architecture concept with independent gates, the PhiFET. We study the coupling effects in nanowires controlled by two independent gates. This architecture, proposed for low-power applications, reveals an excellent control of short-channel effects and improved ION/IOFF ratios...
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