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In PD-SOI the oxide layer between MOSFETs and the underlying silicon substrate presents a thermal resistance that can lead to significant temperature rise for power dissipating devices. This can impact circuit performance and also introduce differences between device characteristics measured under DC conditions and those experienced under "at speed" operating conditions with low duty cycles...
Thermal effects on different tiers of wafer-scale three dimensional (3D) integrated circuits were examined. The temperature was measured using pn diodes, and the heating effects on the characteristics of MOSFETs were compared. It is found that the circuit at the top of the 3D stack is the hottest. Adding metal plugs through the buried oxide or placing metal heat sink at the top surface improves heat...
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