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A linear high output power CMOS direct conversion transmitter for wide band code division multiple access (WCDMA) is presented. Circuit level third order distortion cancellation is applied to driver amplifier to achiever single end output power +9.6 dBm with -43.2 dBc ACLR@5 Mhz and 10% power efficiency at band II. The transmitter is fabricated in 90 nm CMOS technology and die area is 1.1 mm times...
A dual-band transmitter integrated circuit (TxIC), including baseband filter and variable gain amplifier (VGA), upconverter, RF VGA, driver amplifier (DA), is implemented in 0.18 mum CMOS for CDMA applications. The TxIC increases the handset talk time dramatically with the PA-bypass feature. The chip provides more than a total power control range of 80 dB and a fine gain step of 0.25 dB/LSB. The chip...
In this paper, a fully integrated CMOS UWB transmitter is presented. The transmitter consists of a band-notched UWB antenna and a transmitter IC which integrates a pulse generator, a gating signal generator and driver amplifiers. The drive amplifier employs a 2-stage amplifier-a class-E amplifier and a class-A amplifier with switch control, to significantly reduce power consumption. Fabricated using...
This paper presents a novel burst generator architecture dedicated to Ultra Wideband wireless communication systems based on Impulse Radio techniques. Bursts are generated by using an oscillator output signal controlled both in magnitude and phase with a high-speed digital circuit in order to limit output signal bandwidth in accordance with IEEE 802.15.4a standard requirements. The design has been...
A ultra-wideband low noise amplifier (LNA) with integrated notch filter for interference rejection is designed using 0.18-mum CMOS technology. The three-stage LNA employs a current reuse structure to reduce the power consumption and a serial LC circuit with Q-enhancement circuit to produce band rejection in the 5-6 GHz frequency band. The load tank optimization for the current reuse stage is discussed...
A multi-band 900 MHz/1.8 GHz/5.2 GHz low noise amplifier (LNA) which can operate at mobile band of 900 MHz and 1.8 G and WLAN band of 5.2 GHz frequency is proposed. Input matching, noise matching and narrow gain are achieved at three frequency bands by adopting a switched output load and a resistive shunt-feedback circuit. The proposed LNA is designed in TSMC 0.18 um CMOS technology with a supply...
We report an ultra-low voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each...
An RF VCO design optimization strategy to achieve low phase noise and low bias current is presented for a cross-coupled LC-tuned CMOS oscillator topology. The impact of differential pair transistors' mode of operation and loading effects on the oscillator phase noise are investigated. The study shows that an optimal trade-off between thermal-noise-induced phase noise and DC power dissipation can be...
Homodyne receiver structures enable low cost integrated transceivers. A critical requirement of these systems is a high isolation mixer. In this paper, a high LO to RF isolation, double-balanced (Gilbert cell) 60-GHz down-conversion mixer is presented. This mixer achieves a voltage conversion gain better than 2 dB, input-referred IP3 point of -8 dBm and LO to RF isolation greater than -36 dB when...
We present a fully integrated analog path for a 3 G polar transmitter in 90 nm CMOS. It includes a quad band Digitally Controlled Oscillator providing modulation for the phase data and a single stage Digital Pre-Power Amplifier that combines the phase and amplitude signals while providing the dynamic range for WCDMA. The chip, with integrated LDOs, consumes 60 mA from a 1.4 V supply while providing...
This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz - 2.5 GHz with channel bandwidths from 8 KHz to 20 MHz. At 1.8 GHz the receiver...
A highly integrated transceiver for WiMedia UWB applications is presented. Implemented in 130 nm CMOS and operating from 1.2 V and 2.5 V supplies, it features direct conversion transmit and receive paths. Three PLLs with ring-oscillator VCOs are used in a fast-hopping (~2 ns) frequency synthesizer. On-chip calibration is used by several blocks for I/Q mismatch, filter tuning, DC offset cancellation...
This paper describes a direct-conversion RF front-end designed for dual-band WiMedia UWB receiver. The front-end operates in band groups BG1 and BG3. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. As targeted for mobile handset, several issues related to hostile environment are taken into account in this...
This paper presents a new single PLL and single SSB-mixer architecture for a local signal generator of the Mode-1 MB-OFDM UWB systems. Using a VCO running at 8976 MHz and a divide-by-2 circuit, it can provide a 4488-MHz carrier signal with low-spurious levels, which is required to meet the spectrum mask requirements being considered in Japan and Europe. A divide-by-8.5/17 circuit using double-edge...
A UHF RFID reader IC in 0.18 mum CMOS covering the entire 860 MHz to 960 MHz RFID band is presented in this paper. The IC meets the EPC Class-1 Generation-2 and ISO-18000 standards. The transmitter output is +10 dBm and the receiver sensitivity is -96 dBm in listen-before-talk mode (LBT) and -85 dBm in talk-mode (TM). The IC contains 10-bit DACs, pulse-shaping filters, IQ modulator and power amplifier...
We present the design of three key building blocks for UHF-band passive RFID tag chip, i.e., voltage multiplier, ASK demodulator, and internal clock generator. An analysis on a simple equivalent circuit of RFID tag chip for long reading range is presented taking into account the finite turn-on voltage of tag chip. The Schottky diodes used in the passive RFID tag chip were fabricated using titanium...
This paper presents an integrated 2.4 GHz ultra low power CMOS frequency down-converting active mixer based on a single balanced Gilbert-cell resistor-loaded topology where all MOS transistors of mixer core are optimally biased in subthreshold region. At only 500 muW DC power consumption under 1.0 V power supply and small LO power of -9 dBm, this mixer has a measured power conversion gain of 15.7...
A two-antenna array receiver is designed for WLAN application to build a maximum ratio combiner (MRC) system. A new signal-path Cartesian phase generation and combination technique is proposed to shift the RF signal by 22.5 phase steps. The 3 dB improvement in received SNR is achieved in comparison to single path receiver. The 0.29 mm^2 RF paths consumes 30 mW in 0.13 mum CMOS process.
A 5 GHz direct conversion transceiver is fabricated in a 0.13 mum CMOS process for WLAN 802.11a applications. The transmitter achieves -56 dBc LO leakage, -36 dBc sideband rejection, -43 dBc 3rd harmonic suppression at 5.4 GHz, and an EVM of 3.4% at 5.1 GHz with 60 mW power consumption. The receiver achieves 3.3 dB NF, 27 dB conversion gain, -12 dBm IIP3, and a measured 1/f noise corner of 110 kHz...
The design of a traveling wave amplifier (TWA) in a 0.13 mum standard CMOS technology is presented. It is designed to maximize the gain-bandwidth product (GBP). Asymmetric cascode, coplanar wave guide (CPW) and losses compensation technique allow to maximize the TWA GBP. Design and modeling of 90 Omega CPW used to synthesize inductors TWA's lines is presented. Simulations with design kit and developed...
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