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Gate-leakage model of n-Ge MOS capacitor with stacked high-k gate dielectric in inversion region is developed based on energy-band analysis and WKB approximation for hole tunneling. The validity of the model is checked for MOSFET with stacked high-K/interlayer gate dielectric, and simulated results exhibit good agreement with experimental data, indicating the applicability of the model for designing...
Atomic layer deposition (ALD) has emerged as an enabling thin film deposition technology for making semiconductor devices with design rules below 100nm, especially when conformal coatings on high aspect ratio devices are needed. However, ALD is limited in deposition rate. In response to this, recent advances include new capabilities using high productivity thermal ALD, plasma assisted ALD and pulsed...
One of the main requirements for Si-based ultrasmall device is atomic-order control of process technology. Here, we show the concept of atomically controlled processing based on atomic-order surface reaction control. The main idea of the atomic layer approach is the separation of the surface adsorption of reactant gases from the reaction process. Self-limiting formation of 1-3 atomic layers of group...
Plasma-based nanotechnologies benefit the development of deep-submicrometer microelectronic devices. Recent works conducted in our laboratory pertaining to the production of novel silicon-on-insulator (SOI) materials to reduce the self-heating effects and the use of plasma hydrogenation to conduct ion-cutting are described in this invited paper
Continued challenge for higher-performance semiconductor device requires the controlled doping of single-dopant atom to control the electrical properties. Here we report the fabrication of semiconductors with both dopant number and position controlled by using a one-by-one doping technique, which we call "single-ion implantation (SII)". This technique enables us to implant dopant ions one-by-one...
Engineering of point defects semiconductors is important for a variety of applications, including ion implantation/annealing technology and crystal growth. We have developed two new new approaches to controlling point defect behavior - via the surface and photoexcitation. For example, the degree of chemical bond saturation at surfaces can affect dopant activation and transient enhanced diffusion (TED)...
We investigated impacts of halo and deep source/drain junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. The hot carrier degradation was also reduced to an RTA-comparable level by the halo...
Surface states have been one of the fundamental problems in semiconductor technology since the Bardeen era. It is found that a Si(100) surface passivated with a monolayer of selenium can significantly reduce surface states. A number of applications are envisioned for this atomically-engineered surface, including low-resistance ohmic contacts for Si microelectronics, photovoltaics, and high-temperature...
Our newly developed neutral beam (NB) etching could firstly accomplish the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-Fins. The fabricated FinFETs realize higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically flatness of the neutral beam etched surfaces...
Silicidation process and effects of various kinds of additive metals for the improvement of thermal stability of Ni silicide were examined carefully for the 45 nm node. In order to obtain heat resistant NiSi, introduction of various metal layers introduced to top or bottom (interface of Ni/Si) of Ni on Si were investigated. However, we couldn't have any improvement in the thermal stability by any...
Arsenic deposited as a monolayer of pure As on silicon by chemical-vapour-deposition (CVD) epitaxy and capped by an oxide layer has been investigated for the first time as a dopant diffusion source when using anneal temperatures below 900 degC. Schottky diodes of Al to n-and p-type Si with and without such an As-doped surface layer were fabricated. The I-V diode characteristics show that a very small...
This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junctions depth in vertical MOSFETs, it is necessary to look separately at the influence of each junction especially the drain junction on the potential distribution in the channel and hence the SCEs. A self-aligned shallow...
The electrical properties of Ni (Pt)-silicide/Si contact is studied and it is revealed that the Schottky barrier contact obeys a complicated two Gauss distribution. It is demonstrated that the Pt interface layer can not only improve NiSi phase thermal stability but also improve contact homogeneity
In this paper, we investigated the compressive mechanical STI x-stress (in the direction of channel length) on channel width. When the channel width becomes narrower, the compressive STI y-stress effect become more severe and causes STI x-stress has lower effect on NMOS Idsat but has higher effect on PMOS Idsat. This means that the amount of NMOS Idsat decrement due to x-stress become less but the...
In this letter, the material and electrical characteristics of the nickel silicide (NiSi) formed at various RTA temperatures as gate electrode has been studied. By comparing various samples formed at 400 degC, 450 degC, 500 degC, and 600 degC with Vfb-EOT curves, work function and fixed charge, we found that when the RTA temperature is higher than 500 degC the interaction between the NiSi and SiO2 ...
The procedure of low temperature silicon direct bonding (LTSDB) was investigated by bonding surface energy evolving over annealing time. Two kinds of pretreated approaches, O2-plasma exposure and warm HN03 cleaning, were employed. The dynamic analysis of the bonding surface energy exhibits that the bonding procedure is divided into two phases: (1) rapid reaction between OH groups which leads to a...
Lapping is one of the basic procedures in silicon device substrate preparation. There exist excess stress, serious surface scratch, damage and pollution of ion in the procedure of lapping process, so it is necessary to improve the mechanism of lapping through changing the single mechanical action to equilibrium chemical and mechanical action. Under the condition of chemical mechanical action, small...
In this paper, development and application of a direct chemical mechanical polishing (CMP) process for shallow trench isolation (STI) on 200mm wafers using high selectivity ceria-based slurry has been studied for production. Post thickness of silicon nitride and trench oxide showed that new direct CMP process has good within-die range and excellent within-wafer uniformity. Improved planarity and less...
In the further development of chemical mechanical polishing (CMP) process, it needs badly to have a sort of low polydispersion index (PDI) and high purity silica sol nanometer abrasives which can be stable for a long time. In this paper, through a large number of experiments, we have proposed the optimization process schemes and pyramid shape grow mode in preparing large particle size silica sol,...
Atomic scale etching of poly-Si, which can give atomic scale accuracy, was investigated in inductively coupled Ar and He plasmas. Atomic scale etching used a cyclic operation of gas adsorption and ion beam irradiation, which is the same concept as atomic layer etching of single crystal substrates. Cl2 was used as etchant gas, and ions generated from inductively coupled Ar and He plasmas were used...
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