The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, for its better locality than the partial inductance. But few previous works on reluctance extraction took the high frequency effect into account or were efficient enough for 3D complex structure. In this paper, a new reluctance extraction algorithm is presented considering the high frequency effect. Numerical...
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices...
Using a fluorinated high-k/metal gate stack combined with a stress relieved pre-oxide (SRPO) pretreatment before high-k deposition, the authors show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds...
The authors propose a new method to estimate the local dielectric constant of an ultrathin gate insulator film formed on Si substrates by using X-ray photoelectron spectroscopy (XPS). First the authors measure the difference of core-level binding energy shifts for Si 1s and Si 2p, DeltaE1s DeltaE2p, for various Si compounds using high-resolution high-energy synchrotron radiation. the authors find...
The physical and electrical characteristics of high-k (HK) gate dielectric HfLaO were systematically investigated. Incorporation of La in HfO2 can raise the film crystallization temperature from 400degC to 900degC. Moreover, NMOSFETs fabricated with HfLaO gate dielectric exhibit superior electrical performances in terms of threshold voltage (Vth), bias temperature instability (BTI), channel electron...
The authors have achieved a remarkably wide range (~1.2 V) of differences in flatband voltage (Vfb) by using a combination of metal alloy (Pt-W)/La2O3 gate stacks. The controllable range is about 3 times greater than that of Hf-based gate stacks. The wide range of V fb can be maintained even after annealing in forming gas and oxidizing gas ambients. The authors consider that this is attributed to...
Vth control technology of HfSiON gate dielectrics by channel engineering using counter ion implantation method and fluorine or nitrogen ion implantation method are described. Current Ni-FUSI gate technology is also mentioned. Moreover, the authors explain breakdown mechanism of poly-Si/HfSiON/SiO2 gate stacks
Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, the authors have found that the work-function pinning-free-region generally appears due...
Fundamental properties of SiO2 and high-k dielectrics are compared, and the differences can be used to explain physical phenomena in high-k gate stacks. Interfacial reactions and gate Fermi-level pinning arise from the ionic nature of oxygen states in high-k dielectrics. Film crystallization is actually preferable for high-k gate dielectrics due to their lack of bond flexibility, while phase separation...
Oxidation process of HfO2/SiO2/Si(001) structures during annealing in dry oxygen is studied by high-resolution Rutherford backscattering spectroscopy. During the growth of the interfacial SiO2 layer, surface accumulation of Si is observed. This indicates that silicon species are emitted from the SiO 2/Si interface to release the stress induced by oxidation as was predicted by recent theoretical studies...
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, the authors discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict...
In this paper, the authors present a study on the advanced Ni-based fully silicidation (FUSI) technology, which could satisfy various technology requirements of sub-45nm CMOS node, from the device Vt point of view. For n-FETs, adding Yb to Ni FUSI allows for tuning the work function (WF) from midgap (NiSi ~4.72eV) to near n-type band-edge (~4.22eV) on thin SiON. On the pFET, we study the effect of...
Thermal stability of rare earth oxides La2O3/Y2O3 stack structure was studied. X-ray photoelectron spectroscopy (XPS) analysis revealed that Y2O3 layer suppresses the formation of SiO 2 at interface. It was found that mobility degradation in La-based gate dielectric MOSFETs during high temperature annealing can be prevented by inserting a thin Y2O3 interfacial layer
A combinatorial ternary composition spread method, which included continuous ternary and binary compositions, was applied for new materials exploration for the future gate stack structure, rapid estimation of permittivity are carried out by microwave microscope as well as conventional C-V measurement. Structural analyses are performed systematically by combinatorial X-ray diffraction equipment. Higher...
Phase compositions and thermal stability of different TaCx layers deposited by PVD is studied using in-situ high-temperature XRD (HT-XRD). It is found that the phase composition of the as-dep. layers and those during annealing at high temperatures strongly depends on their chemical compositions. Low carbon layers (~Ta4C) are amorphous below 700degC, and crystallize into hexagonal Ta2C in 700-900degC...
In this paper, the authors report the impact of polycrystalline Si structure on the NMOS transistor performance with a HfSiON/Ni-FUSI (fully silicided) gate. For polycrystalline films, as deposited grain structure was predominantly columnar at heater temperatures 690-730degC, except in the presence of hydrogen where the grains assume a random microcrystalline structure. Amorphous film was achieved...
In this work, lanthanum-incorporated refractory metal nitride is investigated as an n-type metal gate electrode with tunable work function. By adding La into HfN metal gate deposited on SiO2 gate dielectric, its gate work function can be tuned from 4.6 eV to 3.9 eV continuously by changing La composition. The authors also report the effective work function of TaN can be tuned to p-type with the incorporation...
The permittivities and the resistance to moisture of LaYOx (LYO) films annealed at 600degC with different Y concentrations are investigated. The permittivities of 40%Y-LYO film and 70%Y-LYO film are higher than 25. The high permittivities come from the well crystallized hexagonal phase of LYO films. For rare earth oxides, the hexagonal phase shows higher permittivity than the cubic phase due to the...
This paper investigates the work function adjustment of Ni-FUSI metal gate. It is obvious that implanting dopant into poly-Si before silicidation can modulate the work function of Ni-FUSI metal gate efficiently. With the implantation of P-type or N-type dopants, such as BF2 and As or P, the work function of Ni-FUSI metal gate can be made higher or lower to satisfy the requirement of PMOS or NMOS
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.