The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction PMOSFETs. This technology reduces thickness of relaxed Si1-xGex epitaxy layer from several micros using UHVCVD to less than 500nm, which improves the heat dissipation of devices. AFM tests of strained Si surface show RMS is less than 1nm and TD density less than...
This paper reviews the applications and potentials of back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) particularly for RF and microwave silicon-device-design enhancement. This type of SOG process gives direct access to the part of the device that is usually connected via the bulk Si, by allowing advanced patterning and contacting of the backside of the wafer (back-wafer)...
The unique device structures of SiGe HBTs, in comparison to Si bipolar homojunction transistors (BJTs), allow us to reconsider the value of common-base (CB) configuration for high-frequency amplifications. In this paper, an omni-directional comparison between common-emitter (CE) and common-base SiGe power HBTs is made. By comparing the power gain, power handling, linearity, noise and stability characteristics...
SiGe HBT technology is now widely considered as a strong contender for broadband wireless communication applications owing to its excellent high-speed characteristics as well as the compatibility with the conventional CMOS technology. In this paper, the performance of modern SiGe HBTs is reviewed in terms of the operation speed, noise, and reliability-related issues
Thin film transistors (TFTs) were fabricated inside a location-controlled, large Si grains through an advanced excimer-laser crystallization with a low temperature process. The field-effect mobility for electrons of the single-grain Si TFTs was as high as 597 cm 2/Vs. CMOS inverters are fabricated inside the location-controlled grain. Propagation delay per stage of 3.1 ns was successfully obtained...
The paper presents a study of threshold voltage for poly-silicon TFTs through a designated experiment with several split conditions on the LDD implantation. Our results show that the abnormality of threshold voltage is caused by the effect of poly grain boundary trapping combining with the LDD condition along the channel edge region. In addition, PLN process is found to be another factor for the threshold...
The influence of doping profile on stability characteristics of SiGe HBTs in both common-emitter and common-base configurations is studied for the first time. It is found that the base doping concentration has a strong influence on the stability characteristics of the common-base configuration. An unconditional stability operation condition for the common-base SiGe HBTs can be potentially realized...
Linearity characteristics and dynamic loadlines of common-emitter (CE) and common-base (CB) configuration SiGe HBTs are analyzed and compared at 6GHz under different bias conditions. It is shown that the CB configuration can have both higher power gain and better linearity than the CE configuration under certain bias conditions. Dynamic loadlines of CE and CB configurations are compared and correlated...
The influences of device size on the small- and large-signal performance of SiGe power HBTs were experimentally studied. It is found that due to the increased parasitics along with the increase of device area, the maximum power gain Gmax (MAG/MSG), maximum oscillation frequency fmax and large-signal power gain continuously decrease with the increase of device size. Furthermore, when the device size...
We present some experimental results showing that two different standard BiCMOS SiGe technologies can operate at 4 K. DC and low frequency measurements were carried out on two SiGe heterojunction bipolar transistors (HBT) of 0.8 mum and 0.35 mum AMS BiCMOS SiGe technologies. We report that for both SiGe HBTs, the transconductance gm increases at cryogenic temperature making possible the use of such...
This paper investigates the electrical properties and the carrier transport mechanisms of nanometer-scale ultra-thin channel (< 3.0nm) poly-Si transistors to be guidelines for future process on device optimization and modeling. Devices used for the study are fabricated with a precise control over the film thickness down to sub-nanometer scale
The microstructures of the Ge-dots/Si multilayered structure films fabricated by metal-induced lateral crystallization (MILC) have been investigated. The micro-Raman spectroscopy, optical microscopy and electron microscopy observations reveal that the crystallized Si film has large leaf-like grains elongated along the lateral crystallization direction, which shows (110) preference. Furthermore, this...
In this work, the paper propose two algorithms to extract the gate-bias-dependent parameters including the RSD, the effective channel length reduction DeltaL, and effective channel mobility mueff for deep submicrometer MOSFETs
To facilitate the use of TIP in circuit implementation, effects of technology scaling on temperature independence point (TIP) in MOS transistor are discussed in this paper. Under technology scaling, location of TIP moves closer to threshold voltage (VT) of a device and starts to appear in PMOS instead of NMOS. Such observations will be explained together with other reported observations (Hisamitsu...
Device physics and design theory of Si, Ge, and Si1-xGe x "complementary vertical dual carrier field effect transistor" (CVDCFET) integrated circuits on insulator for high speed switching and high frequency mixed signal application are studied and compared. The transistor scaling projections of CVDCFET are presented and compared with the scaling projections of CMOS as given in the 2005 edition...
A monolithically integrated optical receiver with spatially modulated light (SML) detector in an unmodified 0.18 mum CMOS technology is presented. The SML-detector exhibits high bandwidth by canceling out the diffusion component and suppressing the slow diffusion tail effect. The receiver comprises a zero-pole cancellation configuration preamplifier stage and a differential amplifier stage. With behavior...
SOI partially depleted NMOS devices with C shape gate, H shape gate, BTS, and T shape gate body contact are fabricated, and their ability to suppress kink effect is studied. C shape gate body contact device expresses better performance to inhibit kink effect than H shape and BTS body contact devices, while T shape device shows the worst performance. As the channel width increases, all partially depleted...
In order to improve the total dose radiation hardness of the buried oxides (BOX) of separation by implanted oxygen (SIMOX) silicon on insulator (SOI),we implanted silicon into the BOX at a dose of l times 1015cm-2 and then annealed at 800 degC in N2 ambience. Partially depleted CMOS/SOI inverters with enclosed-gate structure fabricated on improved SIMOX substrate and standard SIMOX substrate were...
A novel bonding partial SOI structure is described in this paper. The method of LPCVD plus epitaxy-growth bond polysilicon transition layer is proposed, and the structure is achieved. The completeness of this novel wafer structure is greater than 85%. The mean contact specific resistance of Si-Si direct bonding interface is less than 5 times 10-4 ohm.cm2
For power bipolar transistors, the emitter-ballasting-resistor is usually used to improve the thermal stability. However, the ballasting-resistors degrade the output power, power gain, power-added-efficiency (PAE) of the transistor. In this paper, the thermal stability can be improved substantially by adjusting either the spacing or length of the emitter fingers without using ballasting resistors...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.