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In this work, the recessed source/drain (ReS/D) ultra-thin body (UTB) SOI MOS transistor is investigated in detail. Results indicate that the ReS/D structure provides UTB devices with much lower source/drain series resistance than the conventional elevated source/drain (E-S/D) one and thereby alleviates the critical requirement for contact resistivity in sub-50 nm devices. On the other hand, the ReS/D...
A new structure of double gate SB MOSFET in which one of the gates is used to modulate the electric potential distribution (back gate modulated SB MOSFET) is proposed and compared with conventional double gate SB MOSFET and UTB SB MOSFET in terms of off state leakage current, on state current and minimum current, as well as sub-threshold slope(S). The mechanism of SB MOSFET leakage current in off...
Integration of advanced high transport channel materials into Si-based CMOS devices holds great promises for CMOS scaling beyond Moore's Law. In this article, various heteroepitaxy approaches and structures for advanced channel material fabrication in "on-insulator" structures was discuss, including both global and localized epitaxy techniques with strained-Si, Ge, III-V etc. The limits,...
Current status of strained-SOI (sSOI) substrate technology is reviewed along with relevant device-level strain optimization. Smart Cut trade enables to transfer a tensile-strained Si film, grown on Si0.8Ge0.2, onto a 300mm Si wafer, with excellent thickness uniformity and preserved stress. The pile-ups (PUs) have been eliminated and the threading dislocation density has been significantly reduced...
Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge...
Following a brief review of strained silicon technology options, this paper presents results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates...
The integration of 3 major techniques of process induced stress, stress memory technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT), has been demonstrate for advanced CMOS technology. The device performance improvement from each technique and their addability are discussed
For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device's characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A,...
The appropriate external stress can enhance device and circuit performance. The 7.4% speed enhancement is achieved for the 250 nm node ring oscillator under uniaxial tensile strain for mutually perpendicular layout of the NFET and the PFET. The speed enhancement is less than 1.5% for the conventional parallel layout of the NFET and the PFET. The ultra thin strained Si0.2Ge0.8 quantum well channel...
This paper discusses the impact of strain on the low-frequency (LF) noise performance of deep submicrometer MOSFETs. The effect of different strain-engineering approaches, i.e., global, using strained silicon (sSi) substrates on thin SiGe strain-relaxed buffer (SRB) layers or local, relying on recessed SiGe source/drain (S/D) regions or nitride stressors is described. In the case of sSi nMOSFETs,...
This work reviews the current progress in high-mobility strained MOSFETs and covers the latest developments in strain engineering. The paper focuses on the connections between strain, band structure, and channel mobility characteristics. The authors show that accurate band structure calculations are essential to understand the different mechanisms of mobility gain induced by uniaxial and biaxial strain...
In this paper, recent developments in Ge MOS transistor technology and reliability are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on silicon surface passivation. Ge source/drain junction formation of using laser thermal annealing with small dopant loss is then discussed. With high performance Ge p- and n-channel MOSFETs, BTI and charge trapping are characterized
Germanium MOS capacitors with high-quality gate dielectrics are fabricated by novel processing in wet ambients. Wet NO oxidation with wet N2 annealing is used to grow GeON gate dielectric on Ge substrate. As compared to dry NO oxidation, negligible growth of unstable GeOx interlayer and thus a near-perfect GeON dielectric can be obtained. This idea is extended to high-k gate dielectric (HfTiON), which...
Uniaxial strain relaxation of ultra-thin biaxial-tensile SSDOI is realized by ion-implant amorphization and solid phase epitaxy (II/SPE). The selective full amorphization in the thin SSDOI region, between raised source/drain (RSD) and channel, induces uniaxial strain relaxation in the channel. The SSDOI uniaxial strain relaxation enhances PFETs drive current by more than 20%
A mobility model is developed for strained-Si N-MOSFETs accounting for the various mechanisms such as surface roughness scattering, optical phonon scattering and coulomb scattering that cause degradation in effective carrier mobility. The proposed semi-empirical model is in good agreement with experimental data for a wide range of temperatures, doping densities and Ge mole-fractions
Spectroscopic ellipsometry (SE) has been extended to the non-destructive, in-line monitoring of biaxial tensile strain in strained silicon (epsiv-Si). SE data from 250nm - 500nm from three epsiv-Si samples were fitted using a new parametric model for semiconductors. By using the E1 peak shift in the fitted dielectric function spectra, the tensile strain in epsiv-Si can be monitored. Strain values...
Gate-first self-aligned Ge nMOSFET and pMOSFET with metal gate and CVD HfO2 have been successfully fabricated, using a novel laser thermal process (LTP) S/D activation. Compared with conventional rapid thermal annealing (RTA) activation, LTP provides smaller S/D series resistance with shallower junction depth while maintaining good gate stack integrity. Much improved drive current is obtained on Ge...
In this work, it was demonstrated that the Fermi level pinning in poly-Si/HfO2 can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO2 PFET was tuned to -0.81 V in poly-Si/Al2O3/HfO2, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al2O3/HfO2. At the same time, Vth of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, Vth stability was...
Effect of surface roughness on quasi-ballistic transport in nano-scale Ge and Si double-gate (DG) MOSFETs are investigated using 2D full-band self-consistent ensemble Monte Carlo (MC) method based on solving quantum Boltzmann equation (QBE). Results show that the effect of the surface roughness on carrier quasi-ballistic transport in DG nMOSFETs is still significant even when the gate length scales...
Strained-Si n-MOSFET transistors were fabricated on strained Si/uniform relaxed Si0.9Ge0.1/relaxed graded SiGe/Si substrate using reduced pressure chemical vapor deposition (RPCVD) technique. The transistors show a significant mobility enhancement of ~50% compared to control Si n-MOSFET mobilities at low vertical field and at room temperature. The drain current is increased by ~40% for long channel...
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