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Design for manufacturability (DFM) is becoming increasingly important as process geometries shrink. The system-on-chip business model requires high quality, high yielding IP. This paper shows how DFM and DFY are integrated as part of IP delivery, using a set of metrics to identify and fix yield limiters without compromising power, area or performance
Many modern designs have transient and localized failures which can be attributed to excessive instantaneous power consumption known as di/dt or IR drop. IR drop is problematic because power rails may not be sized correctly for the load they must handle in both function and test, and so there might be localized "hot spots". The current technique for mitigating this issue is at design time,...
We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs...
Rewiring has been used extensively for optimizing the area, the power consumption, the delay, and the testability of a circuit. In this work, we demonstrate how rewiring can also be used for reducing the soft error rate (SER). We employ an ATPG-based rewiring method to generate functionally-equivalent yet structurally-different implementations of a logic circuit based on simple transformation rules...
This paper provides some clarity around the buzz words - DFM and DFY. The paper describes the essential DFM methods and how they impact a product's profits. Fortunately, DFM is a broad area that yields incremental benefits from incremental efforts as opposed to something that require a full solution in order to receive benefits. Therefore, a chip design team can use just one technique and begin realizing...
A methodology based on canonical views is developed to facilitate rapid analysis of CMOS characterization and test data for product and process debug. The compressed representations aid in both quantitative and intuitive assimilation of the data, with a focus on model-to-hardware correlation and manufacturing variability
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