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Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultra-low complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than...
Vector quantization (VQ) is a popular image compression method and the encoding speed of VQ is very important to its practical applications. In a conventional encoding process of VQ, because a lot of k-dimensional (k-D) Euclidean distances must be computed so as to find out the best-match for each input vector, VQ is computationally very expensive. In order to avoid immediately computing the real...
A subspace supervised learning algorithm named discriminant non-negative matrix factorization (DNMF) has been recently proposed for classifying human facial expressions. It decomposes images into a set of basis images and corresponding coefficients. Usually, the algorithm starts with random basis image and coefficient initialization. Then, at each iteration, both basis images and coefficients are...
In this paper, an error concealment algorithm is proposed to conceal an entirely lost frame in an H.264/AVC compressed video bitstream. For a lost frame, the algorithm reconstructs the lost motion information of this frame based on its temporal neighbors. The algorithm is block based and thus has low computation and implementation complexity. It is designed for those hard-to-conceal video sequences,...
In our dynamically reconfigurable system model, computation resources are arranged in 2D-plane and each partial task is assigned to computation resources of rectangle-shape for a certain time period. The problem can be regarded as a rectangular box packing problem in 3D-space of 2D-plane and time axis. However, since partial tasks have order constraints, a packing should satisfy the given order constraints...
This paper presents design considerations for cascade sigma-delta modulators (SAMs) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1L-2 expandible SigmaDeltaM is...
In this paper, a 20-Msample/sec and 12-bit resolution sigma delta modulator for 802.11a applications is presented. The distributed feedback with a forward input and resonator feedback schemes are utilized to implement this modulator. The fifth-order 3-bit quantizer single-loop sigma delta modulator achieves 20-MS/s conversion ratio with 74dB of dynamic range and 70dB of peak signal-to-noise-distortion...
H.264 is a very efficient video compression standard. In this paper, a scheme of H.264 encoder implementation based on TMS320C6416 DSP is presented. The structure hardware, the developing platform, the procedure of code immigration and many optimizing methods are discussed. The optimization based on the extended instruction set of C64x for the critical time consuming modules, the scheduling of data...
The data-intensive architecture (DIVA) system incorporates processing-in-memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications. A recently developed PIM chip in TSMC 0.18mum technology incorporates a DDR SDRAM interface for its inclusion...
With the growing complexity of new multimedia applications and the parallel execution enabled by multiprocessor architectures, quality-of-service (QoS) management for modern network-on-chip (NoC) systems becomes relevant. This paper presents an approach for efficient usage of platform resources and simultaneously controlling overall system performance, when multiple applications are active. Therefore,...
This paper examines the nonlinear dynamics of a model of a second order bang-bang phase-locked loop (BB-PLL). Three distinct steady state dynamical patterns (locking, slew-rate limiting and limit cycles) have been observed for this discrete system. A corresponding continuous model of the BB-PLL is established. This paper focuses on the occurrence and the shape of the limit cycles. In particular, equations...
A 120 MHz fractional-N frequency synthesizer was implemented in a standard 0.18mum CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the sigma-delta (SigmaDelta) modulator. Results show the decrease in quantization noise from the 4th order SigmaDelta is 6dB for every two fold...
There has been much interest recently in developing injection locking frequency dividers (ILFDs) since they can consume less power than digital dividers. However, the limited locking range is the main drawback for ILFDs. In this paper, the locking range for an LC oscillator based ILFD is calculated for different divide ratios. The reason that the locking range for dividing by two is much larger than...
A new technique that makes use of a systolic array structure is proposed for solving the common approximate substring (CAS) problem. This approach extends the technique introduced in (Kent et al., 2006) from the computation of the edit-distance between two strings to the more encompassing CAS problem. The technique presented is validated and analyzed through simulation
The design of reconfigurable DeltaSigma modulators requires cumbersome circuit-level simulations. Besides the challenges inherent to high-performance analog-to-digital converter (ADC) design, the gap between system-level specification and circuit-level implementation makes the design even more difficult and inefficient. Circuit macromodels are an efficient way of tackling these problems by speeding...
The primary focus of this paper is the development of a hierarchical symbolic analysis method, which can be used to generate symbolic performance models (SPMs) for large parasitic-inclusive analog circuits. In this paper, a new exact hierarchical technique is proposed, where transfer functions (TF) are synthesized for a general interconnection template (GIT) of two subcircuits. Extremely efficient...
Service restoration problem in distribution systems is formulated as a multiobjective optimization problem which is demanded not only for minimizing the amount of not restored total loads but also for minimizing the number of the switching operations. The solution of the multiobjective optimization problem is usually obtained with a set of Pareto optimal solutions. The Pareto optimal solutions for...
It has been known that every planar 4-graph has a 2-bend 2D orthogonal drawing with the only exception of octahedron, every planar 3-graph has a 1-bend 2D orthogonal drawing with the only exception of K 4, and every outerplanar 3-graph with no triangles has a 0-bend 2D orthogonal drawing. We show in this paper that every series-parallel 4-graph has a 1-bend 2D orthogonal drawing
This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The proposed technique as applied to timing uncertainty mitigation in the signaling of a digital system is presented as an example; the relative phase information is used to minimize the timing skew. The proposed circuit captures...
There are many researches that have been proposed for embedding data into digital video. However, most of those schemes extending data hiding technique for still images to videos by treating each single frame as a still image and embed data in intra-frame. In this paper, we propose an effective data-hiding scheme that embeds data in digital videos using the phase angle of the motion vector of the...
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