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In preceding papers, a genetic algorithm was developed for the design and optimization of the noise transfer function in higher-order Sigma-Delta A/D and D/A converters having cascade-of-resonators (COR), cascade-of-integrators (COI), and combined cascade-of-integrators-cum-resonators (CRI) configurations. This paper presents a two-stage genetic-algorithm for the optimization of the constituent multiplier...
The "software radio (SWR)" concept has become a topic of widespread interest for reconfigurable mobile architecture design. It is seen as the next evolutionary step in the mobile communications. In this context of SWR, a way to decrease the runtime of the software reconfiguration and to optimize the sharing between the software and the hardware of the execution platform called "parametrization"...
A novel single CMOS chip contains both the actuation and sensing parts is presented. Experimental results showed that the proposed chip can inline process the trapping, levitation, sensing and characterize biocells. Moreover, the proposed chip can deal with the biological systems at the cell level and it can extract real time information about the biological cells behaviors using direct measurements
This paper considers some little discussed basic aspects of bit error probability and bit error rate in the context of spread spectrum shift keying binary communication systems. It points out that bit error rate is an average of bit error probability and suggests further ways of using the distribution of bit error probability to give alternative and complementary measures of performance of binary...
A current-mode "even"-nth-order OTA-C elliptic filter with the minimum components is presented in this paper. The filter, designed by the analytical synthesis method, is the counterpart of the recently reported current-mode "odd"-nth-order filter and features both current-mode signals and the important criteria of single ended input OTAs and grounded capacitors. Only (3n)/2 single-value...
An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 muW at sub-1V. The DSP consumes only 10 muW at 0...
Pass transistor logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs, and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned reduced ordered binary decision diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In...
This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of CAVLC decoding process to efficient skip possible processes if none needed to be decoded, and can decode multiple symbols in sign and run before stage. The proposed design just needs average 90 cycles for one MB decoding, which...
We present a hybrid opto-electronic system capable of improving the performance of on-chip electrical fanout architectures. Our opto-electronic system employs a layer of optical fanout and utilizes the electrical isolation between the receiving nodes. Through our proof-of-concept links, we show a 15% latency reduction for links as short as 200mum and 50% reduction at 2mm
The performance of a receiver front-end limits the quality and range of the given communication link. An appropriate design based on well-defined system parameters and architecture can make a huge difference in the performance, cost and marketability of the entire system. In particular, there is a need for improved digital automatic gain control (AGC) for use in multi input multi output orthogonal...
In this paper, we address the problem of FSM state assignment to minimize area and power. The objectives are targeted as single/independent as well as multi-objective optimization (MOP) problems. Methods for estimating area and power of an FSM are presented. A fuzzy-based aggregation function is employed to combine the two objectives. The work employs genetic algorithm for search space exploration...
In this paper, an efficient moving object segmentation algorithm in the wavelet domain is proposed using three successive frames. The change detection method, which employs fuzzy C-means clustering technique to classify motion features of four wavelet sub-bands, is used twice to separate significant change pixels in the wavelet domain from the background. After applying the intersect operation, the...
Some digital signal processing applications, such as FFT's, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that...
This paper presents circuits for conversion from radix-2 signed-digit residue numbers to binary form. Four reverse converters for combined RNS/SD number systems based on different moduli sets are presented. Implementations are compared with respect to timing, area and area-delay products. Finite impulse response (FIR) filters are used as reference designs in order to evaluate the performance of RNS/SD...
The work concerns one of the most important problems in the field of design, modeling and simulation of modern electronic embedded systems at a very high level of abstraction - i.e. system level modeling. The approach to modeling of SoC in SystemC (2003) is presented. The author formulates philosophy of the PROLOG expert system that aids the process of models generation. Main assumptions of the library...
The work area of a team of small robots is limited by their inability to traverse a very common obstacle: stairs. We present a complete integrated control architecture and communication strategy for a system of reconfigurable robots that can climb stairs. A modular robot design is presented which allows the robots to dynamically reconfigure to traverse certain obstacles. This work investigates the...
This paper introduces a positive-feedback self-biasing technique for operational amplifiers (op-amps) which enables their power consumption to adapt to their environment: The power consumption of one of our op-amps scales almost linearly with load capacitance, input signal frequency, and output signal swing. Our op-amp is primarily intended for low power switched-capacitor applications. A voltage...
This paper presents a new speech enhancement scheme to meet the strong demand for quality noise reduction at very low signal-to-noise ratios (SNR). The proposed method generalizes the spectral subtraction algorithm to correlate time-frequency domain information based on the auditory masking property. The psycho acoustic model is integrated with the unvoiced speech enhancement algorithm to improve...
Model order reduction (MOR) has proven to be an effective tool in combatting the computational complexities that arise from the simulation of large interconnect networks. Furthermore, parametric model order reduction (PMR) was recently developed for extending this concept to optimization and design space exploration of interconnect networks. The difficulty with current PMR methods is that the reduced...
This paper presents a novel LC oscillator, capable of operating at frequencies beyond 100 GHz in a standard 0.13 mum CMOS process. A new phase noise reduction technique using higher order LC filter is introduced and theories are discussed. Custom designed coplanar waveguides from 3D electromagnetic simulation are employed, and a corresponding circuit model is extracted from an S-parameter optimization...
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